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? 2012 freescale semiconductor, inc. all rights reserved. freescale semiconductor data sheet: technical data document number: imx51cec rev. 6, 10 /2012 imx51 package information plastic package case 2058 13 x 13 mm, 0.5 mm pitch case 2017 19 x 19 mm, 0.8 mm pitch ordering information see ta b l e 1 on page 3 for ordering information. 1 introduction the i.mx51 multimedia applications processors represent freescale semiconductor?s latest addition to a growing family of multimedia-focused products that offer high performance processing and are optimized for lowest power consumption. the i.mx51 processors feature freescale?s advanced and power-efficient implementation of the arm cortex?-a8 core, which operates at speeds as high as 800 mhz. up to 200 mhz ddr2 and mobile ddr dram clock rates are supported. these devices are suitable for applications such as the following: ? netbooks (web tablets) ? nettops (internet desktop devices) ? mobile internet devices (mid) ? portable media players (pmp) ? portable navigation devices (pnd) ? high-end pdas ? gaming consoles ? automotive navigation and entertainment (see automotive data sheet, imx51aec) i.mx51 applications processors for consumer and industrial products 1. introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.1. ordering information . . . . . . . . . . . . . . . . . . . . . . . 3 1.2. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2. features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.1. special signal considerations . . . . . . . . . . . . . . . 12 3. iomux configuration for boot media . . . . . . . . . . . . . . . 14 3.1. nand . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.2. sd/mmc iomux pin configuration . . . . . . . . . . . 15 3.3. i 2 c iomux pin configuration . . . . . . . . . . . . . . . . 15 3.4. ecspi/cspi iomux pin configuration . . . . . . . . 16 3.5. wireless external interface module (weim) . . . . 16 3.6. uart iomux pin configuration . . . . . . . . . . . . . 16 3.7. usb-otg iomux pin configuration . . . . . . . . . . 16 4. electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . 17 4.1. chip-level conditions . . . . . . . . . . . . . . . . . . . . . 17 4.2. supply power-up/power-down requirements and restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.3. i/o dc parameters . . . . . . . . . . . . . . . . . . . . . . . . 24 4.4. output buffer impedance characteristics . . . . . . 31 4.5. i/o ac parameters . . . . . . . . . . . . . . . . . . . . . . . . 35 4.6. module timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 4.7. external peripheral interfaces . . . . . . . . . . . . . . . 74 5. package information and contact assignments . . . . . 153 5.1. 13 x 13 mm package information . . . . . . . . . . . . 153 5.2. 19 x 19 mm package information . . . . . . . . . . . . 173 5.3. 13 13 mm, 0.5 pitch ball map . . . . . . . . . . . . . 191 5.4. 19 x 19 mm, 0.8 pitch ball map . . . . . . . . . . . . . 195 6. revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
i.mx51 applications processors for consumer and industrial products, rev. 6 2 freescale semiconductor introduction features include the following: ? smart speed technology ?the heart of the i.mx51 processors is a level of power management throughout the device that enables the rich suite of multimedia features and peripherals to achieve minimum system power consumption in both active and various low-power modes. smart speed technology enables the designer to deliver a feature -rich product that requires levels of power that are far less than typical industry expectations. ? applications processor ?the i.mx51 processors boost the capabilities of high-tier portable applications by providing for the ever-increasing mips needs of operating systems and games. freescale?s dynamic voltage and fr equency scaling (dvfs) allows the device run at much lower voltage and frequency with suffic ient mips for tasks such as audio decode resulting in significant power reduction. ? multimedia powerhouse ?the multimedia performance of the i.mx51 processors is boosted by a multi-level cache system and further enhanced by a multi-standard hardware video codec, autonomous image processing unit, sd and hd720p triple video (tv) encoder with triple video dac, neon (including advanced simd, 32-bit single-precision floating point support and vector floating point co-processor), and a programmable smart dma (sdma) controller. ? powerful graphics acceleration ?graphics is the key to mobile game navigation, web browsing, and other applications. the i.mx51 processors provide two independent, integrated graphics processing units: opengl es 2.0 3d graphics accelerator (27 mtri/s, 166 mpix/s) and openvg 1.1 2d graphics accelerator (166 mpix/s). ? interface flexibility ?the i.mx51 processor interface supports connection to all popular types of external memories: ddr2, mobile ddr, nor flash, psram, cellular ram, nand flash (mlc and slc), and onenand. designers seeking to provide products that deliver a rich multimedia experience find a full suite of on-chip peripherals: lcd controller and cmos sensor interface, high-speed usb on-the-go with phy, and three high-speed usb hosts, multiple expansion card ports (high-speed mmc/sdio host and others), 10/100 ethe rnet controller, and a variety of other popular interfaces (pata, uart, i 2 c, i 2 s serial audio, and sim card, among others). ? increased security ?because the need for advanced security for mobile devices continues to increase, the i.mx51 processors deliver hardware-enabled security features that enable secure e-commerce, digital rights management (drm), information encryption, secure boot, and secure software downloads. for detailed information about the mx51 security features contact your freescale representative.
introduction i.mx51 applications processors for consumer and industrial products, rev. 6 freescale semiconductor 3 1.1 ordering information table 1 provides the ordering information. table 1. ordering information 1 1 for junction temperature (tj) maximum ratings, see table 11, "absolute maximum ratings," on page 18 . part number 2, 2 because of an order from the united states international trade commission, bga-packaged product lines and part numbers indicated here currently are not available from freescale for import or sale in the united states prior to september 2010: indicated by the icon ( ! ) mask set features case temperature range ( c) package 3 3 case 2017 and case 2058 are rohs compliant, lead-free, msl = 3. mcimx512cjm6c m77x no hardware video codecs no hardware graphics accelerators ?40 to 95 19 x 19 mm, 0.8 mm pitch bga case 2017 mcimx512djm8c m77x no hardware video codecs no hardware graphics accelerators ?20 to 85 19 x 19 mm, 0.8 mm pitch bga case 2017 mcimx513cjm6c m77x no hardware graphics accelerators ?40 to 95 19 x 19 mm, 0.8 mm pitch bga case 2017 mcimx513djm8c m77x no hardware graphics accelerators ?20 to 85 19 x 19 mm, 0.8 mm pitch bga case 2017 mcimx515cjm6c m77x full specification ?40 to 95 19 x 19 mm, 0.8 mm pitch bga case 2017 mcimx515djm8c m77x full specification ?20 to 85 19 x 19 mm, 0.8 mm pitch bga case 2017 mcimx515dvk8c ! m77x full specification ?20 to 85 13 x 13 mm, 0.5 mm pitch bga case 2058
i.mx51 applications processors for consumer and industrial products, rev. 6 4 freescale semiconductor introduction 1.2 block diagram figure 1 shows the functional modules of the processor. figure 1. functional block diagram application processor domain (ap) external memory i/f smart dma (sdma) sdma peripherals ap peripherals arm cortex a8 internal ram ddr memory nor/nand flash audio/power management arm cortex a8 l1 i/d cache ssi esdhc (4) spba ecspi (1 of 2) uart sim camera 1 platform p-ata rf/if ics sim bluetooth wlan usb-otg mmc/sdio keypad neon and vfp l2 cache etm, cti0,1 xvr jtag irda xvr access. conn. video lcd display 2 lcd display 1 camera 2 proc. unit (vpu) timers cspi uart (3) gpt pwm (2) epit (2) gpiox32 (4) wdog (2) 1-wire i 2 c(2),hsi 2 c iomuxc iim audmux kpp sjc axi and ahb switch fabric boot rom ssi (3) rtic scc srtc csu fuse box clock and reset pll (3) ccm gpc src debug dap tpiu graphics tv-out tv encoder firi memory sahara lite security tzic usb phy spdif tx image processing subsystem battery ctrl device usb dev/host gps ethernet usb otg + 3 hs ports digital audio ata hdd cti (2) ecspi (2 ) xtalosc (128 kbytes) (128 kbytes) camp (2) fec 3d graphics proc unit (gpu) 2d graphics proc unit (gpu2d)
features i.mx51 applications processors for consumer and industrial products, rev. 6 freescale semiconductor 5 2features the i.mx51 processor contains a large number of digital and analog modules that are described in table 2 . table 2. i.mx51 digital and analog modules block mnemonic block name subsystem brief description 1-wire 1-wire interface connectivity peripherals 1-wire support provided for interfacing with an on-board eeprom, and smart battery interfaces, for example: dallas ds2502. arm cortex?-a8 arm cortex?-a8 platform arm the arm cortex?-a8 core platform consists of the arm cortex?-a8 processor version r2p5 (with trustzone) and its essential sub-blocks. it contains the level 2 cache controller, 32 kbyte l1 instruction cache, 32 kbyte l1 data cache, and a 256 kbyte l2 cache. the platform also contains an event monitor and debug modules. it also has a neon co-processor with simd media processing architecture, register file with 32 64-bit general-purpose registers, an integer execute pipeline (alu, shift, mac), dual, single-precision floating point execute pipeline (fadd, fmul), load/store and permute pipeline and a non-pipelined vector floating point (vfp) co-processor (vfpv3). audio subsystem audio subsystem multimedia peripherals the elements of the audio subsystem are three synchronous serial interfaces (ssi1-3), a digital audio mux (audmux), and digital audio out (spdif tx). see the specific interface listings in this table. audmux digital audio mux multimedia peripherals the audmux is a programmable interconnect for voice, audio, and synchronous data routing between host serial interfaces (for example, ssi1, ssi2, and ssi3) and peripheral serial interfaces (audio and voice codecs). the audmux has seven ports (three internal and four external) with identical functionality and programming models. a desired connectivity is achieved by configuring two or more audmux ports. ccm gpc src clock control module global power controller system reset controller clocks, resets, and power control these modules are responsible for clock and reset distribution in the system, and also for system power management. the modules include three plls and a frequency pre-multiplier (fpm). cspi-1, ecspi-2 ecspi-3 configurable spi, enhanced cspi connectivity peripherals full-duplex enhanced synchronous serial interface, with data rate up to 66.5 mbit/s (for ecspi, master mode). it is configurable to support master/slave modes, four chip selects to support multiple peripherals. csu central security unit security the central security unit (csu) is responsible for setting comprehensive security policy within the i.mx51 platform, and for sharing security information between the various security modules. the security control registers (scr) of the csu are set during boot time by the high assurance boot (hab) code and are locked to prevent further writing. debug system debug system system control the debug system provides real-time trace debug capab ility of both instructions and data. it supports a trace protocol that is an integral part of the arm real time debug solution (realview). real-time tracing is controlled by specifying a set of triggering and filtering resources, which include address and data comparators, cross-system triggers, counters, and sequencers.
i.mx51 applications processors for consumer and industrial products, rev. 6 6 freescale semiconductor features emi external memory interface connectivity peripherals the emi is an external and internal memory interface. it performs arbitration between multi-axi masters to multi-memory controllers, divided into four major channels: fast memories (mobile ddr, ddr2) channel, slow memories (nor-flash/psram/nand-flash and so on) channel, internal memory (ram, rom) channel and graphical memory (gmem) channel. in order to increase the bandwidth performance, the emi separates the buffering and the arbitration between different channels so parallel accesses can occur. by separating the channels, slow accesses do not interfere with fast accesses. emi features: ? 64-bit and 32-bit axi ports ? enhanced arbitration scheme for fast channel, including dynamic master priority, and taking into account which pages are open or closed and what type (read or write) was the last access ? flexible bank interleaving ? supports 16/32-bit mobile ddr up to 200 mhz sdclk (mddr400) ? supports 16/32-bit (non-mobile) ddr2 up to 200 mhz sdclk (ddr2-400) ? supports up to 2 gbit mobile ddr memories ? supports 16-bit (in muxed mode only) psram memories (sync and async operating modes), at slow frequency, for debugging purposes ? supports 32-bit nor-flash memories (only in muxed mode), at slow frequencies for debugging purposes ? supports 4/8-ecc, page sizes of 512 bytes, 2 kbytes and 4 kbytes ? nand-flash (including mlc) ? multiple chip selects ? enhanced mobile ddr memory controller, supporting access latency hiding ? supports watermarking for security (internal and external memories) ? supports samsung onenand ? (only in muxed i/o mode) epit-1 epit-2 enhanced periodic interrupt timer timer peripherals each epit is a 32-bit ?set and forget? timer that starts counting after the epit is enabled by software. it is capable of providing precise interrupts at regular intervals with minimal processor intervention. it has a 12-bit prescaler for division of input clock frequency to get the required time setting for the interrupts to occur, and counter values can be programmed on the fly. esdhc-1 esdhc-2 esdhc-3 enhanced multi-media card/ secure digital host controller connectivity peripherals the features of the esdhc module, when serving as host, include the following: ? conforms to sd host controller standard specification version 2.0 ? compatible with the mmc system specification version 4.2 ? compatible with the sd memory card specification version 2.0 ? compatible with the sdio card specification version 1.2 ? designed to work with sd memory, minisd memory, sdio, minisdio, sd combo, mmc and mmc rs cards ? configurable to work in one of the following modes: ?sd/sdio 1-bit, 4-bit ?mmc 1-bit, 4-bit, 8-bit ? full-/high-speed mode ? host clock frequency variable between 32 khz to 52 mhz ? up to 200 mbps data transfer for sd/sdio cards using four parallel data lines ? up to 416 mbps data transfer for mmc cards using eight parallel data lines table 2. i.mx51 digital and analog modules (continued) block mnemonic block name subsystem brief description
features i.mx51 applications processors for consumer and industrial products, rev. 6 freescale semiconductor 7 esdhc-4 (muxed with p-ata) enhanced multi-media card/ secure digital host controller connectivity peripherals can be configured as esdhc (see above) and is muxed with the p-ata interface. fec fast ethernet controller connectivity peripherals the ethernet media access controller (mac) is designed to support both 10 mbps and 100 mbps ethernet/ieee std 802.3? networks. an external transceiver interface and transceiver function are required to complete the interface to the media. firi fast infra-red interface connectivity peripherals fast infra-red interface gpio-1 gpio-2 gpio-3 gpio-4 general purpose i/o modules system control peripherals these modules are used for general purpose input/output to external ics. each gpio module supports up to 32 bits of i/o. gpt general purpose timer timer peripherals each gpt is a 32-bit ?free-running? or ?set and forget? mode timer with a programmable prescaler and compare and capture register. a timer counter value can be captured using an external event, and can be configured to trigger a capture event on either the leading or trailing edges of an input pulse. when the timer is configured to operate in ?set and forget? mode, it is capable of providing precise interrupts at regular intervals with minimal processor intervention. the counter has output compare logic to provide the status and interrupt at comparison. this timer can be configured to run either on an external clock or on an internal clock. gpu graphics processing unit multimedia peripherals the gpu provides hardware acceleration for 2d and 3d graphics algorithms with sufficient processor power to run desk-top quality interactive graphics applications on displays up to hd720 resolution. it supports color representation up to 32 bits per pixel. the gpu with its 128 kbyte memory enables high performance mobile 3d and 2d vector graphics at rates up to 27 mtriangles/sec, 166 mpixels/sec, 664 mpixels/sec (z). gpu2d graphics processing unit-2d ver. 1 multimedia peripherals the gpu2d provides hardware acceleration for 2d graphic algorithms with sufficient processor power to run desk-top quality interactive graphics applications on displays up to hd720 resolution. i 2 c-1 i 2 c-2 hs-i 2 c i 2 c interface connectivity peripherals i 2 c provides serial interface for controlling peripheral devices. data rates of up to 400 kbps are supported by two of the i 2 c ports. data rates of up to 3.4 mbps (i 2 c specification v2.1) are supported by the hs-i 2 c. note: see the errata for the hs-i 2 c in the i.mx51 chip errata. the two standard i 2 c modules have no errata. table 2. i.mx51 digital and analog modules (continued) block mnemonic block name subsystem brief description
i.mx51 applications processors for consumer and industrial products, rev. 6 8 freescale semiconductor features iim ic identification module security the ic identification module (iim) provides an interface for reading, programming, and/or overriding identification and control information stored in on-chip fuse elements. the module supports electrically programmable poly fuses (e-fuses). the iim also provides a set of volatile software-accessible signals that can be used for software control of hardware elements not requiring non-volat ility. the iim provides the primary user-visible mechanism for interfacing with on-chip fuse elements. among the uses for the fuses are unique chip identifiers, mask revision numbers, cryptographic keys, jtag secure mode, boot characteristics, and various control signals requiring permanent non-volat ility. the iim also provides up to 28 volatile control si gnals. the iim consists of a master controller, a software fuse value shadow cache, and a set of registers to hold the values of signals visible outside the module. iomuxc iomux control system control peripherals this module enables flexible i/o multiplexing. each i/o pad has default as well as several alternate functions. the alternate functions are software configurable. ipu image processing unit multimedia peripherals ipu enables connectivity to displays and image sensors, relevant processing and synchronization. it supports two display ports and two camera ports, through the following interfaces. ? legacy interfaces ? analog tv interfaces (through a tv encoder bridge) the processing includes: ? support for camera control ? image enhancement: color adjustment and gamut mapping, gamma correction and contrast enhancement, sharpening and noise reduction ? video/graphics combining ? support for display backlight reduction ? image conversion?resizing, rotation, inversion and color space conversion ? synchronization and control capabilities, allowing autonomous operation. ? hardware de-interlacing support kpp keypad port connectivity peripherals the kpp supports an 8 8 external keypad matrix. the kpp features are as follows: ? open drain design ? glitch suppression circuit design ? multiple keys detection ? standby key press detection p-ata (muxed with esdhc-4 parallel ata connectivity peripherals the p-ata block is an at attachment host interface. its main use is to interface with hard disc drives and optical disc drives. it interfaces with the ata-5 (udma-4) compliant device over a number of ata signals. it is possible to connect a bus buffer between the host side and the device side. this is muxed with esdhc-4 interfaces. pwm-1 pwm-2 pulse width modulation connectivity peripherals the pulse-width modulator (pwm) has a 16-bit counter and is optimized to generate sound from stored sample audio images. it can also generate tones. the pwm uses 16-bit resolution and a 4 x 16 data fifo to generate sound. ram 128 kbytes internal ram internal memory unified ram, can be split between secure ram and non-secure ram rom 36 kbytes boot rom internal memory supports secure and regular boot modes table 2. i.mx51 digital and analog modules (continued) block mnemonic block name subsystem brief description
features i.mx51 applications processors for consumer and industrial products, rev. 6 freescale semiconductor 9 rtic real time integrity checker security protecting read-only data from modification is one of the basic elements in trusted platforms. the run-time integrity checker v3 (rticv3) module, is a data monitoring device responsible for ensuring that memory content is not corrupted during program execution. the rticv3 mechanism periodically checks the integrity of code or data sections during normal os run-time execution without interfering with normal operation. the rticv3?s purpose is to ensure the integrity of the peripheral memory contents, protect against unauthorized external memory elements replacement, and assist with boot authentication. sahara lite sahara security accelerator lite security sahara (symmetric/asymmetric hashing and random accelerator) is a security co-processor. it implements symmetric encryption algorithms, (aes, des, 3des, and rc4), public key algorithms, hashing algorithms (md5, sha-1, sha-224, and sha-256), and a hardware random number generator. it has a slave ip bus interface for the host to write configuration and command information, and to read status information. it also has a dma controller, with an ahb bus interface, to reduce the burden on the host to move the required data to and from memory. scc security controller security the security controller is a security assurance hardware module designed to safely hold sensitive data such as encryption keys, digital right management (drm) keys, passwords, and biometrics reference data. the scc monitors the system?s alert signal to determine if the data paths to and from it are secure?that is, cannot be accessed from outside of the defined security perimeter. if not, it erases all sensitive data on its internal ram. the scc also features a key encryption module (kem) that allows non-volatile (external memory) storage of any sensitive data that is temporarily not in use. the kem utilizes a device-specific hidden secret key and a symmetric cryptographic algorithm to transform the sensitive data into encrypted data. sdma smart direct memory access system control peripherals the sdma is multi-channel flexible dma engine. it helps in maximizing system performance by off loading various cores in dynamic data routing. the sdma features list is as follows: ? powered by a 16-bit instruction-set micro-risc engine ? multi-channel dma supports up to 32 time-division multiplexed dma channels ? 48 events with total flexibility to trigger any combination of channels ? memory accesses including linear, fifo, and 2d addressing ? shared peripherals between arm cortex?-a8 and sdma ? very fast context-switching with two-level priority-based preemptive multi-tasking ? dma units with auto-flush and prefetch capability ? flexible address management for dma transfers (increment, decrement, and no address changes on source and destination address) ? dma ports can handle unit-directional and bi-directional flows (copy mode) ? up to 8-word buffer for configurable burst transfers for emi ? support of byte-swapping and crc calculations ? a library of scripts and api are available sim subscriber identity module interface connectivity peripherals the sim is an asynchronous interface with additional features for allowing communication with smart cards conforming to the iso 7816 specification. the sim is designed to facilitate communication to sim cards or pre-paid phone cards. table 2. i.mx51 digital and analog modules (continued) block mnemonic block name subsystem brief description
i.mx51 applications processors for consumer and industrial products, rev. 6 10 freescale semiconductor features sjc secure jtag interface system control peripherals jtag manipulation is a known hacker?s method of executing unauthorized program code, getting control over secure applications, and running code in privileged modes. the jtag port provides a debug access to several hardware blocks including the arm processor and the system bus. the jtag port must be accessible during platform initial laboratory bring-up, manufacturing tests and troubleshooting, as well as for software debugging by authorized entities. however, in order to properly secure the system, unauthorized jtag usage should be strictly forbidden. in order to prevent jtag manipulation while allowing access for manufacturing tests and software debugging, the i.mx51 processor incorporates a mechanism for regulating jtag access. the i.mx51secure jtag controller provides four different jtag security modes that can be selected via e-fuse configuration. spba shared peripheral bus arbiter system control peripherals spba (shared peripheral bus arbiter) is a two-to-one ip bus interface (ip bus) arbiter. spdif sony philips digital interface multimedia peripherals a standard digital audio transmission protocol developed jointly by the sony and philips corporations. only the transmitter functi onality is supported. srtc secure real time clock security the srtc incorporates a special system state retention register (ssrr) that stores system parameters during system shutdown modes. this register and all srtc counters are powered by dedicated supply rail nvcc_srtc_pow. the nvcc_srtc_pow can be energized even if all other supply rails are shut down. this register is helpful for storing warm boot parameters. the ssrr also stores the system security state. in case of a security violation, the ssrr mark the event (security violation indication). ssi-1 i2s/ssi/ac97 interface connectivity peripherals the ssi is a full-duplex synchronous interface used on the i.mx51 processor to provide connectivity with off-chip audio peripherals. the ssi supports a wide variety of protocols (ssi normal, ssi network, i2s, and ac-97), bit depths (up to 24 bits per word), and clock/frame sync options. each ssi has two pairs of 8x24 fifos and hardware support for an external dma controller in order to minimize its impact on system performance. the second pair of fifos provides hardware interleaving of a second audio stream, which reduces cpu overhead in use cases where two timeslots are being used simultaneously. ssi-2 ssi-3 tve tv encoder multimedia the tve is implemented in conjunction with the image processing unit (ipu) allowing handheld devices to display captured still images and video directly on a tv or lcd projector. it supports the following analog video outputs: composite, s-video, and component video up to hd720p/1080i. tzic trustzone aware interrupt controller arm/control the trustzone interrupt controller (tzic) collects interrupt requests from all i.mx51 sources and routes them to the arm core. each interrupt can be configured as a normal or a secure interrupt. software force registers and software priority masking are also supported. table 2. i.mx51 digital and analog modules (continued) block mnemonic block name subsystem brief description
features i.mx51 applications processors for consumer and industrial products, rev. 6 freescale semiconductor 11 uart-1 uart-2 uart-3 uart interface connectivity peripherals each of the uart modules supports the following serial data transmit/receive protocols and configurations: ? 7 or 8 bit data words, 1 or 2 stop bits, programmable parity (even, odd, or none) ? programmable baud rates up to 4 mhz. this is a higher max baud rate relative to the 1.875 mhz, which is stated by the tia/eia-232-f standard and previous freescale uart modules. ? 32-byte fifo on tx and 32 half-word fifo on rx supporting auto-baud ? irda 1.0 support (up to sir speed of 115200 bps) ? option to operate as 8-pins full uart, dce, or dte usb usb 2.0 high-speed otg and 3x hosts connectivity peripherals usb-otg contains one high-speed otg module, which is internally connected to the on-chip hs usb phy. there are an additional three high-speed host modules that require external usb phys. vpu video processing unit multimedia peripherals a high-performing video processing unit (vpu), which covers many sd-level video decoders and sd-level encoders as a multi-standard video codec engine as well as several important video processing such as rotation and mirroring. vpu features: ? mpeg-4 decode: 720p, 30 fps, simple profile and advanced simple profile ? mpeg-4 encode: d1, 25/30 fps, simple profile ? h.263 decode: 720p, 30 fps, profile 3 ? h.263 encode: d1, 25/30 fps, profile 3 ? h.264 decode: 720p, 30 fps, baseline, main, and high profile ? h.264 encode: d1, 25/30 fps, baseline profile ? mpeg-2 decode: 720p, 30 fps, mp-ml ? mpeg-2 encode: d1, 25/30 fps, mp-ml (in software with partial acceleration in hardware) ? vc-1 decode: 720p, 30 fps, simple, main, and advanced profile ? divx decode: 720p, 30 fps versions 3, 4, and 5 ? rv10 decode: 720p, 30 fps ? mjpeg decode: 32 mpix/s ? mjpeg encode: 64 mpix/s wdog-1 watch dog timer peripherals the watch dog timer supports two comparison points during each counting period. each of the comparison points is configurable to evoke an interrupt to the arm core, and a second point evokes an external event on the wdog line. wdog-2 (tz) watch dog (trustzone) timer peripherals the trustzone watchdog (tz wdog) timer module protects against trustzone starvation by providing a method of escaping normal mode and forcing a switch to the tz mode. tz starvation is a situation where the normal os prevents switching to the tz mode. this situation should be avoided, as it can compromise the system?s security. once the tz wdog module is activated, it must be serviced by tz software on a periodic basis. if servicing does not take place, the timer times out. upon a time-out, the tz wdog asserts a tz mapped interrupt that forces switching to the tz mode. if it is still not served, the tz wdog asserts a security violation signal to the csu. the tz wdog module cannot be programmed or deactivated by a normal mode sw. xtalosc crystal oscillator i/f clocking the xtalosc module allows connectivity to an external crystal. table 2. i.mx51 digital and analog modules (continued) block mnemonic block name subsystem brief description
i.mx51 applications processors for consumer and industrial products, rev. 6 12 freescale semiconductor features 2.1 special signal considerations table 3 lists special signal considerations for the i.mx51. the signal names are listed in alphabetical order. the package contact assignments are found in section 5, ?package information and contact assignments.? signal descriptions are defined in the i.mx51 multimedia applications processor reference manual (mcimx51rm). table 3. special signal considerations signal name remarks ckih1, ckih2 inputs feeding camps (clock amplifiers) that have on-chip ac coupling precluding the need for external coupling capacitors. the camps are enabled by default, but the main clocks feeding the on-chip clock tree are sourced from xtal/extal by default. optionally, the use of a low jitter external oscillators to feed ckih1 or ckih2 (while not required) can be an advantage if low jitter or special frequency clock sources are required by modules driven by ckih1 or ckih2. see ccm chapter in the i.mx51 multimedia applications processor reference manual (mcimx51rm) for details on the respective clock trees. after initialization, the camps could be disabled (if not used) by ccm registers (ccr campx_en field). if disabled, the on-chip camp output is low; the input is irrelevant. if unused, the user should tie ckih1/ckih2 to gnd for best practice. clk_ss clock source select is the input that selects the default reference clock source providing input to the dplls. to use a reference in the megahertz range per table 8, tie clk_ss to gnd to select extal/xtal. to use a reference in the kilohertz range per table 59, tie clk_ss to nvcc_per3 to select ckil. after initialization, the reference clock source can be changed (initial setting is overwritten). note: because this input has a keeper circuit, freescale recommends tying this input to directly to gnd or nvcc_per3. if a series resistor is used its value must be 4.7 k . comp the user should bypass this reference with an external 0.1 f capacitor tied to gnd. if tv out is not used, float the comp contact and ensure the dacs are powered down. note: previous engineering samples required this reference to be bypassed to a positive supply. fastr_ana and fastr_dig these signals are reserved for freescale manufacturing use only. user must tie both connections to gnd. gpanaio this signal is reserved for freescale manufacturing use only. users should float this output. gpio_nand this is a general-purpose input/output (gpio3_12) on the nvcc_nandf_a power rail. iob, iog, ior, iob_back, iog_back, and ior_back these signals are analog tv outputs that should be tied to gnd when not being used. jtag_ nnnn the jtag interface is summarized in ta b l e 4 . use of external resistors is unnecessary. however, if external resistors are used, the user must ensure that the on-chip pull-up/down configuration is followed. for example, do not use an external pull down on an input that has on-chip pull-up. jtag_tdo is configured with a keeper circuit such that the floating condition is eliminated if an external pull resistor is not present. an external pull resistor on jtag_tdo is detrimental and should be avoided. jtag_mod is referenced as sjc_mod in the i.mx51 multimedia applications processor reference manual (mcimx51rm). both names refer to the same signal. jtag_mod must be externally connected to gnd for normal operation. termination to gnd through an external pull-down resistor (such as 1 k ) is allowed. nc these signals are no connect (nc) and should be floated by the user.
features i.mx51 applications processors for consumer and industrial products, rev. 6 freescale semiconductor 13 pmic_int_req when using the mc13892 power management ic, the pmic_int_req high-priority interrupt input on i.mx51 should be either floated or tied to nvcc_srtc_pow with a 4.7 k to 68 k resistor. this avoids a continuous current drain on the real-time clock backup battery due to a 100 k on-chip pull-up resistor. pmic_int_req is not used by the freescale bsp (board support package) software. the bsp requires that the general-purpose int output from the mc13892 be connected to the i.mx51 gpio input gpio1_8 configured to cause an interrupt that is not high-priority. the original intent was for pmic_int_req to be connected to a circuit that detects when the battery is almost depleted. in this case, the i/o must be configured as alternate mode 0 (alt0 = power fail). por_b this cold reset negative logic input resets all modules and logic in the ic. note: the por_b input must be immediately asserted at power-up and remain asserted until after the last power rail is at its working voltage. reset_in_b this warm reset negative logic input resets all modules and logic except for the following: ? test logic (jtag, iomuxc, dap) ?srtc ? memory repair ? configuration of memory repair per fuse settings ? cold reset logic of wdog ? some wdog logic is only reset by por_b. see wdog chapter in i.mx51 multimedia applications processor reference manual (mcimx51rm) for details. rrefext determines the reference current for the usb phy bandgap reference. an external 6.04 k 1% resistor to gnd is required. sgnd, svcc, and svddgp these sense lines provide the ability to sense actual on-chip voltage levels on their respective supplies. sgnd monitors differentials of the on-chip ground versus an external power source. svcc monitors on-chip vcc, and svddgp monitors vddgp. freescale recommends connection of the svcc and svddgp signals to the feedback inputs of switching power-supplies or to test points. str this signal is reserved for freescale manufacturing use. the user should float this signal. test_mode test_mode is for freescale factory use only. this signal is internally connected to an on-chip pull-down device. users must either float this signal or tie it to gnd. vref when using vref with ddr-2 i/o, the nominal 0.9 v reference voltage must be half of the nvcc_emi_dram supply. the user must tie vref to a precision external resistor divider. use a 1 k 0.5% resistor to gnd and a 1 k 0.5% resistor to nvcc_emi_dram. shunt each resistor with a closely-mounted 0.1 f capacitor. to reduce supply current, a pair of 1.5 k 0.1% resistors can be used. using resistors with recommended tolerances ensures the 2% vref tolerance (per the ddr-2 specification) is maintained when four ddr-2 ics plus the i.mx51 are drawing current on the resistor divider. note: when vref is used with mddr this signal must be tied to gnd. vrefout this signal determines the triple video dac (tvdac) reference voltage. the user must tie vrefout to an external 1.05 k 1% resistor to gnd. table 3. special signal considerations (continued) signal name remarks
i.mx51 applications processors for consumer and industrial products, rev. 6 14 freescale semiconductor iomux configuration for boot media 3 iomux configuration for boot media the information provided in this section describes the contacts assigned for each type of bootable media. it also includes data about the clocks used during boot flow and their frequencie s. signals that can be multiplexed appear in tables throughout this section. see the iomuxc chapter in the i.mx51 multimedia applications processor reference manual (mcimx51rm) for details about how to program the iomux controller. vreg this regulator is no longer used and should be floated by the user. xtal/extal the user should tie a fundamental-mode crystal across xtal and extal. the crystal must be rated for a maximum drive level of 100 w or higher. an esr (equivalent series resistance) of 80 or less is recommended. freescale bsp (board support package) software requires 24 mhz on extal. the crystal can be eliminated if an external 24 mhz oscillator is available. in this case, extal must be directly driven by the external oscillator and xtal is floated. the extal signal level must swing from nvcc_osc to gnd. if the clock is used for usb, then there are strict jitter requirements: < 50 ps peak-to-peak below 1.2 mhz and < 100 ps peak-to-peak above 1.2 mhz for the usb phy. the cosc_en bit in the ccm (clock control module) must be cleared to put the on-chip oscillator circuit in bypass mode which allows extal to be externally driven. cosc_en is bit 12 in the ccr register of the ccm. table 4. jtag controller interface summary jtag i/o type on-chip termination jtag_tck input 100 k pull-down jtag_tms input 47 k pull-up jtag_tdi input 47 k pull-up jtag_tdo 3-state output keeper jtag_trstb input 47 k pull-up jtag_de_b input/open-drain output 47 k pull-up jtag_mod input 100 k pull-up table 3. special signal considerations (continued) signal name remarks
iomux configuration for boot media i.mx51 applications processors for consumer and industrial products, rev. 6 freescale semiconductor 15 3.1 nand the nand flash controller (nfc) signals are not configured in the iomux. the nfc interface uses dedicated contacts on the ic. 3.2 sd/mmc iomux pin configuration table 5 shows the sd/mmc iomux pin configuration. only dat0 is available when the sd/mmc is used for boot. the remaining lines (dat1?dat7) are not available. 3.3 i 2 c iomux pin configuration the contacts assigned to the signals used by the three i 2 c modules is shown in table 6 . table 5. sd/mmc iomux pin configuration signal esdhc1 esdhc2 esdhc3 esdhc4 clk sd1_clk.alt0 sd2_clk.alt0 nandf_rdy_int.alt5 nandf_cs2.alt5 cmd sd1_cmd.alt0 sd2_cmd.alt0 nandf_cs7.alt5 nandf_rb1.alt5 dat0 sd1_data0.alt0 sd2_data0.alt0 nandf_we_b.alt2 nandf_cs3.alt5 dat1 n/a 1 1 n/a in the rom code indicates the pins are not available. n/a n/a n/a dat2 n/a n/a n/a n/a cd/dat3 sd1_data3.alt0 sd2_data3.alt0 nandf_rb0.alt5 nandf_cs6.alt5 dat4 n/a n/a n/a n/a dat5 n/a n/a n/a n/a dat6 n/a n/a n/a n/a dat7 n/a n/a n/a n/a table 6 . i 2 c iomux pin configuration signal hsi 2 ci 2 c1 i 2 c2 sda i2c1_dat.alt0 i2c1_dat.alt0 gpio1_3.alt2 scl i2c1_clk.alt0 i2c1_clk.alt0 gpio1_2.alt2
i.mx51 applications processors for consumer and industrial products, rev. 6 16 freescale semiconductor iomux configuration for boot media 3.4 ecspi/cspi iomux pin configuration the contacts assigned to the signals used by the three spi modules is shown in table 7 . 3.5 wireless external interface module (weim) the weim interface signals are not configured in the iomux. the weim interface uses dedicated contacts on the ic. 3.6 uart iomux pin configuration the contacts assigned to the signals used by the three uart modules are shown in ta ble 8 . 3.7 usb-otg iomux pin configuration the interface signals of the utmi phy are not configured in the iomux. the utmi phy interface uses dedicated contacts on the ic. table 7. spi iomux pin configuration signal ecspi1 ecspi2 cspi miso cspi1_miso.alt0 nandf_rb3.alt2 usbh1_nxt.alt1 mosi cspi1_mosi.alt0 nandf_d15.alt2 usbh1_dir.alt1 rdy cspi1_rdy.alt0 nandf_rb1.alt2 usbh1_stp.alt1 sclk cspi1_sclk.alt0 nandf_rb2.alt2 usbh1_clk.alt1 ss0 n/a 1 1 n/a in the rom code indicates the pins are not available. n/a n/a ss1 n/a n/a usbh1_data5.alt1 ss2 n/a n/a n/a ss3 n/a n/a n/a table 8. uart iomux pin configuration signal uart1 uart2 uart3 txd uart1_txd.alt0 uart2_txd.alt0 uart3_txd.alt1 rxd uart1_rxd.alt0 uart2_rxd.alt0 uart3_rxd.alt1 cts uart1_cts.alt0 usbh1_data0.alt1 key_col5.alt2 rts uart1_rts.alt0 usbh1_data3.alt1 key_col4.alt2 table 9. ulpi phy iomux pin configuration signal ulpi phy usb_pwr gpio1_8.alt1 usb_oc gpio1_9.alt1
electrical characteristics i.mx51 applications processors for consumer and industrial products, rev. 6 freescale semiconductor 17 note usb otg ulpi port is not supported and it is not functional. on-chip phy is always used for the otg port. 4 electrical characteristics this section provides the device and module-level electrical characteristics for the i.mx51 processor. 4.1 chip-level conditions this section provides the device-level electrical characteristics for the ic. see table 10 for a quick reference to the individual tables and sections. caution stresses beyond those listed under table 11 may cause permanent damage to the device. these are stress ratings only. functional operation of the device at these or any other conditions beyond those indicated under table 13 is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. usbotg_clk eim_cs4.alt2 usbotg_nxt eim_cs3.alt2 usbotg_stp eim_cs2.alt2 usbotg_dat0 eim_d24.alt2 usbotg_dat1 eim_d25.alt2 usbotg_dat2 eim_d26.alt2 usbotg_dat3 eim_d27.alt2 usbotg_dat4 eim_d28.alt2 usbotg_dat5 eim_d29.alt2 usbotg_dat6 eim_d30.alt2 usbotg_dat7 eim_d31.alt2 table 10. i.mx51 chip-level conditions for these characteristics, ? topic appears ? table 11, ?absolute maximum ratings? on page 18 ta b l e 1 2 , ? thermal resistance data ? on page 18 ta b l e 1 3 , ? i.mx51 operating ranges ? on page 19 ta b l e 1 4 , ? interface frequency ? on page 21 table 9. ulpi phy iomux pin configuration (continued) signal ulpi phy
i.mx51 applications processors for consumer and industrial products, rev. 6 18 freescale semiconductor electrical characteristics table 12 provides the thermal resistance data. table 11. absolute maximum ratings parameter description symbol min max unit peripheral core supply voltage vcc ?0.3 1.35 v arm core supply voltage vddgp ?0.3 1.15 v supply voltage (uhvio, i 2 c) supplies denoted as i/o supply ?0.5 3.6 v supply voltage (except uhvio, i 2 c) supplies denoted as i/o supply ?0.5 3.3 v usb vbus vbus ? 5.25 v input/output voltage range v in /v out ?0.5 ovdd + 0.3 1 1 the term ovdd in this section refers to the associated supply rail of an input or output. the association is described in table 128 and ta b l e 1 3 1 . the maximum range can be superseded by the dc tables. v esd damage immunity: v esd v human body model (hbm) charge device model (cdm) ? ? 2000 500 storage temperature range t storage ?40 125 o c junction temperature (mcimx51xd?consumer) t j ?1 0 5 o c junction temperature (mcimx51xc?industrial) t j ?1 0 5 o c table 12. thermal resistance data rating board symbol value unit junction to case 1 , 19 x 19 mm package 1 rjc-x per jedec 51-12: the junction-to-case thermal resistance. the ?x? indicates the case surface where t case is measured and through which 100% of the junction power is forced to flow due to the cold plate heat sink fixture placed either at the top (t) or bottom (b) of the package, with no board attached to the package. ?r jc 6 c / w junction to case 1 , 13 x 13 mm package ? r jc 6 c / w
electrical characteristics i.mx51 applications processors for consumer and industrial products, rev. 6 freescale semiconductor 19 table 13 shows the i.mx51 operating ranges. table 13. i.mx51 operating ranges symbol parameter minimum 1 nominal 2 maximum 1 unit vddgp mcimx51xd products (consumer) arm core supply voltage 0 f arm 167 mhz 0.8 0.85 1.15 v arm core supply voltage 167 < f arm 800 mhz 1.05 1.1 1.15 v arm core supply voltage stop mode 0.8 0.85 1.15 v vddgp mcimx51xc products (industrial) arm core supply voltage 0 < f arm 600 mhz 0.95 1.0 1.10 v arm core supply voltage stop mode 0.90 0.95 1.05 v vcc mcimx51xd products (consumer) peripheral supply voltage high performance mode (hpm) the clock frequencies are derived from axi and ahb buses using 133 or 166 mhz (as needed). the ddr clock rate is 200 mhz. note: for detailed information about the use of 133 or 166 mhz clocks, see i.mx51 multimedia applications processor reference manual (mcimx51rm). 1.175 1.225 1.275 v peripheral supply voltage low performance mode (lpm) the clock frequencies are derived from axi and ahb buses at 44 mhz and a ddr clock rate of ddr clock/3. ddr2 does not support frequencies below 125 mhz per jedec. 1.00 1.05 1.275 v peripheral supply voltage?stop mode 0.9 0.95 1.275 v vcc mcimx51xc products (industrial) peripheral supply voltage high performance mode (hpm) the clock frequencies are derived from axi and ahb buses using 133 or 166 mhz (as needed). the ddr clock rate is 200 mhz. note: for detailed information about the use of 133 or 166 mhz clocks, see i.mx51 multimedia applications processor reference manual (mcimx51rm). 1.175 1.225 1.275 v peripheral supply voltage?stop mode 0.90 0.95 1.275 v vdda memory arrays voltage?run mode 1.15 1.20 1.275 v memory arrays voltage?stop mode 0.9 0.95 1.275 v vdd_dig_pll_a vdd_dig_pll_b pll digital supplies 1.15 1.2 1.35 v vdd_ana_pll_a vdd_ana_pll_b pll analog supplies 1.75 1.8 1.95 v
i.mx51 applications processors for consumer and industrial products, rev. 6 20 freescale semiconductor electrical characteristics nvcc_emi nvcc_per5 nvcc_per10 nvcc_per11 nvcc_per12 nvcc_per13 nvcc_per14 gpio emi supply and additional digital power supplies. 1.65 1.875 or 2.775 3.1 v nvcc_ipux 3 nvcc_per3 nvcc_per8 nvcc_per9 gpio ipu supply and additional digital power supplies. 1.65 1.875 or 2.775 3.1 v nvcc_emi_dram ddr and fuse read supply 1.65 1.8 1.95 v vdd_fuse 4 fusebox program supply (write only) 3.0 ? 3.3 v nvcc_nandf_x 5 nvcc_per15 nvcc_per17 ultra high voltage i/o (uhvio) supplies ? v uhvio_l 1.65 1.875 1.95 uhvio_h 2.5 2.775 3.1 uhvio_uh 3.0 3.3 3.6 nvcc_usbphy nvcc_osc usb_phy analog supply, oscillator analog supply 6 2.25 2.5 2.75 v tvdac_dhvdd, nvcc_tv_back, ahvddrgb tve-to-dac level shifter supply, cable detector supply, analog power supply to rgb channel 2.69 2.75 2.91 v nvcc_hs4_1 nvcc_hs4_2 nvcc_hs6 nvcc_hs10 hs-gpio additional digital power supplies 1.65 ? 3.1 v nvcc_i2c i 2 c and hs-i 2 c i/o supply 7 1.65 1.875 1.95 v 2.7 3.0 3.3 nvcc_srtc_ pow srtc core and i/o supply (lvio) 1.1 1.2 1.3 v vdda33 usb phy i/o analog supply 3.0 3.3 3.6 v vbus see tab le 1 1 and table 126 for details. this is not a power supply. ?? ?? t c case temperature (mcimx51xd?consumer) ?20 ? 85 o c case temperature (mcimx51xc?industrial) ?40 ? 95 o c 1 voltage at the package power supply contact must be maintained between the minimum and maximum voltages. the design must allow for supply tolerances and system voltage drops. 2 the nominal values for the supplies indicate the target setpoint for a tolerance no tighter than 50 mv. use of supplies with a tighter tolerance allows reduction of the setpoint with commensurate power savings. 3 the nvcc_ipux rails are isolated from one another. this allows the connection of different supply voltages for each one. for example, nvcc_ipu2 can operate at 1.8 v while nvcc_ipu4 operates at 3.0 v. table 13. i.mx51 operating ranges (continued) symbol parameter minimum 1 nominal 2 maximum 1 unit
electrical characteristics i.mx51 applications processors for consumer and industrial products, rev. 6 freescale semiconductor 21 4.1.1 supply current table 15 shows the fuse supply current. table 16 shows the current core consumption (not including i/o) of the i.mx51. 4 in read mode, freescale recommends vdd_fuse be floated or grounded. tying vdd_fuse to a positive supply (3.0 v?3.3 v) increases the possibility of inadvertently blowing fuses and is not recommended. 5 the nand flash supplies are composed of three groups: a, b, and c. each group can be powered with a different supply voltage. for example, nvcc_nandf_a = 1.8 v, nvcc_nandf_b = 3.0 v, nvcc_nandf_c = 2.7 v. 6 the analog supplies should be isolated in the application design. use of series inductors is recommended. 7 operation of the hs-i 2 c and i 2 c is not guaranteed when operated between the supply voltages of 1.95 to 2.7 v. table 14. interface frequency parameter description symbol min max unit jtag: tck operating frequency f tck see table 99, "jtag timing," on page 132 mhz ckil: operating frequency f ckil see table 74, "fpm specifications," on page 82 khz ckih: operating frequency f ckih see table 47, "camp electrical parameters (ckih1, ckih2)," on page 48 mhz xtal oscillator f xtal 22 27 mhz table 15. fuse supply current 1 1 the read current of approximately 5 ma is derived from the ddr supply (nvcc_emi_dram). description symbol min typ max unit efuse program current. 2 current required to program one efuse bit: the associated vdd_fuse supply per table 13 . 2 the current i program is only required during program time. i program ? 60 120 ma table 16. i.mx51 stop mode current and power consumption mode condition supply nominal unit stop mode ? external reference clocks gated ? power gating for arm and processing units ? stop mode voltage vddgp = 0.85 v, vcc = 0.95 v, vdda = 0.95 v arm core in srpg mode l1 and l2 caches power gated ipu in s&rpg mode vpu and gpu in pg mode all plls off, all ccm-generated clocks off ckil input on with 32 khz signal present all modules disabled usbphy pll off external (mhz) crystal and on-chip oscillator powered down (sbyos bit asserted) no external resistive loads that cause current flow standby voltage allowed (vstby bit is asserted) t a = 25 c vddgp 0.18 ma vcc 0.35 vdda 0.15 nvcc_osc 0.012 total 0.66 mw
i.mx51 applications processors for consumer and industrial products, rev. 6 22 freescale semiconductor electrical characteristics stop mode ? external reference clocks gated ? power gating for arm and processing units ? hpm voltage vddgp = 1.1 v, vcc = 1.225 v, vdda = 1.2 v arm core in srpg mode l1 and l2 caches power gated ipu in s&rpg mode vpu and gpu in pg mode all plls off, all ccm-generated clocks off ckil input on with 32 khz signal present all modules disabled. usbphy pll off external (mhz) crystal and on-chip oscillator powered down (sbyos bit asserted) no external resistive loads that cause current flow t a = 25 c vddgp 0.24 ma vcc 0.45 vdda 0.2 nvcc_osc 0.012 total 1.09 mw stop mode ? external reference clocks enabled ? power gating for arm and processing units ? hpm voltage vddgp = 1.1 v, vcc = 1.225 v, vdda = 1.20 v arm core in srpg mode l1 and l2 caches power gated ipu in s&rpg mode vpu and gpu in pg mode all plls off, all ccm-generated clocks off ckil input on with 32 khz signal present all modules disabled usbphy pll off external (mhz) crystal and on-chip oscillator pow- ered and generating reference clock no external resistive loads that cause current flow t a = 25 c vddgp 0.24 ma vcc 0.45 vdda 0.2 nvcc_osc 1.5 to t a l 4 . 8 m w stop mode ? external reference clocks enabled ? no power gating for arm and processing units ? hpm voltage vddgp = 1.1 v, vcc = 1.225 v, vdda = 1.2 v all plls off, all ccm-generated clocks off ckil input on with 32 khz signal present all modules disabled usbphy pll off external (mhz) crystal and on-chip oscillator powered and generating reference clock no external resistive loads that cause current flow t a = 25 c vddgp 50 ma vcc 2 vdda 1.15 nvcc_osc 1.5 to t a l 6 3 m w table 16. i.mx51 stop mode current and power consumption (continued) mode condition supply nominal unit
electrical characteristics i.mx51 applications processors for consumer and industrial products, rev. 6 freescale semiconductor 23 4.1.2 usb phy current consumption table 17 shows the usb phy current consumption. 4.2 supply power-up/power-down requirements and restrictions the system design must comply with the power-up and power-down sequence guidelines as described in this section to guarantee reliable operation of the de vice. any deviation from these sequences may result in the following situations: ? excessive current during power-up phase ? prevention of the device from booting ? irreversible damage to the i.mx51 processor (worst-case scenario) table 17. usb phy current consumption parameter conditions typical @ 25 c max unit analog supply vdda33 (3.3 v) full speed rx 5.5 6 ma tx 7 8 high speed rx 5 6 tx 5 6 analog supply nvcc_usbphy (2.5 v) full speed rx 6.5 7 ma tx 6.5 7 high speed rx 12 13 tx 21 22 digital supply vcc (1.2 v) full speed rx 6 7 ma tx 6 7 high speed rx 6 7 tx 6 7 vdda33 + nvcc_usbphy + vcc suspend 50 100 a
i.mx51 applications processors for consumer and industrial products, rev. 6 24 freescale semiconductor electrical characteristics 4.2.1 power-up sequence figure 2 shows the power-up sequence. figure 2. power-up sequence note the por_b input must be immediately asserted at power-up and remain asserted until after the last power rail is at its working voltage. for more information on power up, see i.mx51 power-up sequence (an4053). 4.3 i/o dc parameters this section includes the dc parameters of the following i/o types: ? general purpose i/o and high-speed general purpose i/o (gpio/hsgpio) ? double data rate 2 (ddr2) ? low voltage i/o (lvio) ? ultra high voltage i/o (uhvio) ? high-speed i 2 c and i 2 c ? enhanced secure digital host controller (esdhc) ahvddrgb nvcc_tv_back tvdac_dhvdd vdd_dig_pll_a/b vdd_ana_pll_a/b nvcc_osc nvcc_usbphy vdda33 nvcc_emi_dram nvcc_srtc_pow vdda nvcc_nandf_x nvcc_per15 nvcc_per17 nvcc_hs4_1 nvcc_hs4_2 nvcc_hs6 nvcc_hs10 nvcc_perx 2 nvcc_emi nvcc_ipu nvcc_i2c vddgp 4 vdd_fuse 1 vcc 1. vdd_fuse should only be powered when writing. 2. nvcc_perx refers to nvcc_per 3, 5, 8, 9, 10, 11, 12, 13, 14. 3. no power-up sequence dependencies exist between the supplies shown in the block diagram shaded in gray. 4. there is no requirement for vddgp to be preceded by any other power supply other than nvcc_srtc_pow. 5. if all of the uhvio supplies (nvcc_nandfx, nvcc_per15 and nvcc_per17) are less than 2.75 v then there is no requirement on the power up sequence order between nvcc_emi_dram and the uhvio supplies. however, if the voltage is 2.75 v and above, then nvcc_emi_dram needs to power up before the uhvio supplies as shown here.
electrical characteristics i.mx51 applications processors for consumer and industrial products, rev. 6 freescale semiconductor 25 note the term ovdd in this section refers to the associated supply rail of an input or output. the association is shown in table 128 and table 131 . 4.3.1 gpio/hsgpio dc parameters the parameters in table 18 are guaranteed per the operating ranges in table 13 , unless otherwise noted. table 18. gpio/hsgpio dc electrical characteristics parameter symbol test conditions min typ max unit high-level output voltage voh iout = -1 ma ovdd ?0.15 ? ovdd + 0.3 v low-level output voltage vol iout = 1ma ? ? 0.15 v high-level output current ioh vout = 0.8 ovdd low drive medium drive high drive max drive ?1.9 ?3.7 ?5.2 ?6.6 ?? ma low-level output current iol vout = 0.2 ovdd low drive medium drive high drive max drive 1.9 3.7 5.2 6.6 ?? ma high-level dc input voltage 1 1 to maintain a valid level, the transition edge of the input must sustain a constant slew rate (monotonic) from the current dc level through to the target dc level, vil or vih. monotonic input transition time is from 0.1 ns to 1 s. vih ? 0.7 ovdd ? ovdd v low-level dc input voltage 1 vil ? 0 ? 0.3 ovdd v input hysteresis vhys ovdd = 1.875 ovdd = 2.775 0.25 0.34 0.45 ?v schmitt trigger vt+ 1, 2 2 hysteresis of 250 mv is guaranteed over all operating conditions when hysteresis is enabled. vt+ ? 0.5ovdd ? ? v schmitt trigger vt- 1, 2 vt- ? ? ? 0.5 ovdd v input current (no pull-up/down) iin vin = ovdd or 0 ? ? see note 3 3 i/o leakage currents are listed in tab le 2 5 . ? input current (22 k pull-up) iin vin = 0 ? ? 161 a input current (47 k pull-up) iin vin = 0 ? ? 76 a input current (100 k pull-up) iin vin = 0 ? ? 36 a input current (100 k pull-down) iin vin = ovdd ? ? 36 a keeper circuit resistance ? ovdd = 1.875v ovdd = 2.775v ? ? 22 17 ? ? k
i.mx51 applications processors for consumer and industrial products, rev. 6 26 freescale semiconductor electrical characteristics 4.3.2 ddr2 i/o dc parameters the parameters in table 19 are guaranteed per the operating ranges in table 13 , unless otherwise noted. 4.3.3 low voltage i/o (lvio) dc parameters the parameters in table 20 are guaranteed per the operating ranges in table 13 , unless otherwise noted. table 19. ddr2 i/o dc electrical parameters parameters symbol test conditions min max unit high-level output voltage voh ? ovdd ? 0.28 ? v low-level output voltage vol ? ? 0.28 v output minimum source current ioh ovdd = 1.7 v vout = 1.42 v ?13.4 ? ma output min sink current iol ovdd = 1.7 v vout = 0.28 v 13.4 ? ma dc input logic high vih ? ovdd/2 + 0.125 ovdd + 0.3 v dc input logic low vil ? ?0.3 ovdd/2 ? 0.125 v input voltage range of each differential input vin ? ?0.3 ovdd + 0.3 v differential input voltage required for switching vid ? 0.25 ovdd + 0.6 v termination voltage vtt vtt tracking ovdd/2 ovdd/2 ? 0.04 ovdd/2 + 0.04 v input current (no pull-up/down) iin vi = 0 vi = ovdd ? ? see note 1 1 i/o leakage currents are listed in ta ble 2 5 . ? table 20. lvio dc electrical characteristics dc electrical characteristics symbol test conditions min typ max unit high-level output voltage voh iout = ?1 ma ovdd ? 0.15 ? ? v low-level output voltage vol iout = 1 ma ? ? 0.15 v high-level output current i ioh vout = 0.8 ovdd low drive medium drive high drive max drive ?2.1 ?4.2 ?6.3 ?8.4 ?? ma low-level output current i iol vout = 0.2 ovdd low drive medium drive high drive max drive 2.1 4.2 6.3 8.4 ?? ma high-level dc input voltage 1 vih ? 0.7 ovdd ? ovdd v low-level dc input voltage 1 vil ? 0 ? 0.3 ovdd v input hysteresis vhys ovdd = 1.875 ovdd = 2.775 0.35 0.62 1.27 ?v
electrical characteristics i.mx51 applications processors for consumer and industrial products, rev. 6 freescale semiconductor 27 4.3.4 ultra-high voltage i/o (uhvio) dc parameters the parameters in table 21 are guaranteed per the operating ranges in table 13 , unless otherwise noted. schmitt trigger vt+ 1, 2 vt+ ? 0.5 ovdd ? ? v schmitt trigger vt? 1, 2 vt? ? ? ? 0.5 ovdd v input current (no pull-up/down) iin vi = 0 or ovdd ? ? see note 3 ? input current (22 k pull-up) iin vi = 0 ? ? 161 a input current (47 k pull-up) iin vi = 0 ? ? 76 a input current (100 k pull-up) iin vi = 0 ? ? 36 a input current (100 k pull-down) iin vi = ovdd ? ? 36 a keeper circuit resistance ? ovdd = 1.875 v ovdd = 2.775 v ? ? 22 17 ? ? k 1 to maintain a valid level, the transition edge of the input must sustain a constant slew rate (monotonic) from the current dc level through to the target dc level, vil or vih. monotonic input transition time is from 0.1 ns to 1 s. 2 hysteresis of 250 mv is guaranteed over all operating conditions when hysteresis is enabled. 3 i/o leakage currents are listed in ta b l e 2 5 . table 21. uhvio dc electrical characteristics dc electrical characteristics symbol test conditions min typ max unit high-level output voltage voh iout = ?1ma ovdd?0.15 ? ? v low-level output voltage vol iout = 1ma ? ? 0.15 v high-level output current, low voltage mode ioh_lv vout = 0.8 ovdd low drive medium drive high drive ?2.2 ?4.4 ?6.6 ?? ma high-level output current, high voltage mode ioh_hv vout = 0.8 ovdd low drive medium drive high drive ?5.1 ?10.2 ?15.3 ?? ma low-level output current, low voltage mode iol_lv vout = 0.2 ovdd low drive medium drive high drive 2.2 4.4 6.6 ?? ma low-level output current, high voltage mode iol_hv vout = 0.2 ovdd low drive medium drive high drive 5.1 10.2 15.3 ?? ma high-level dc input voltage 1 , 2 vih ? 0.7 ovdd ? ovdd v low-level dc input voltage 2,3 vil ? 0 ? 0.3 ovdd v table 20. lvio dc electrical characteristics (continued) dc electrical characteristics symbol test conditions min typ max unit
i.mx51 applications processors for consumer and industrial products, rev. 6 28 freescale semiconductor electrical characteristics the uhvio type of i/o cells have to be configured properly according to their supply voltage level, in order to prevent permanent damage to them and in order to not degrade their timing performance. the hve control bit of the i/o cell (in iomux control registers) should be set to 1 for low voltage operation and to 0 for high voltage operation. the hve bit should be set as follows: ? hve = 0: high output voltage mode (3.0v to 3.6v) ? hve = 1: low output voltage mode (1.65v to 3.1v) this is related to power domains, such as nvcc_nandf, nvcc_per15, and nvcc_per17. if hve bit is not set properly when high voltage level is applied for long durations, it may cause permanent damage over a period of time, causing reduced timing performance of the pad. similarly, not setting hve bit properly for low voltage will degrade pad timing performance. the below discussion clarifies concerns about boot-up period. the hve bit is set, by default, to 1 for low voltage operation. as a result, there might be a short period conflict between the hve bit value and the applied vo ltage. this conflict is acceptable under the following conditions: input hysteresis vhys low voltage mode high voltage mode 0.38 0.95 ?0.43 1.33 v schmitt trigger vt+ 2,3 vt+ ? 0.5ovdd ? ? v schmitt trigger vt? 2,4 vt? ? ? ? 0.5 ovdd v input current (no pull-up/down) iin vin = 0 vin = ovdd ? ? see note 4 ? input current (22 k pull-up) iin vin = 0 ? ? 202 a input current (75 k pull-up) iin vin = 0 ? ? 61 a input current (100 k pull-up) iin vin = 0 ? ? 47 a input current (360 k pull-down) iin vin = ovdd ? ? 5.7 a keeper circuit resistance ? na ? 17 ? k 1 to maintain a valid level, the transitioning edge of the input must sustain a constant slew rate (monotonic) from the current dc level through to the target dc level, vil or vih. monotonic input transition time is from 0.1 ns to 1 s. 2 overshoot and undershoot conditions (transitions above ovdd and below ovss) on switching pads must be held below 0.6 v, and the duration of the overshoot/undershoot must not exceed 10% of the system clock cycle. overshoot/undershoot must be controlled through printed circuit board layout, transmission line impedance matching, signal line termination, or other method s. non-compliance to this specification may affect device reliability or cause permanent damage to the device. 3 hysteresis of 250 mv is guaranteed over all operating conditions when hysteresis is enabled. 4 i/o leakage currents are listed in ta b l e 2 5 . table 21. uhvio dc electrical characteristics (continued) dc electrical characteristics symbol test conditions min typ max unit
electrical characteristics i.mx51 applications processors for consumer and industrial products, rev. 6 freescale semiconductor 29 ? the uhvio pads receive supply voltage up to 3.3v (3.6v max); however, the pads do not toggle during the boot-up sequence (using another interface as a boot code source), for boot-up period of about 22 msec. ? the uhvio pads receive up to 3.15v (3.3v max) and are used for accessing the boot code, for boot-up period of about 11 msec. in any case, it is recommended to try to minimize the duration of this period and reduce the amount of toggling on the pads as much as possible. for this, it is recommended to add proper hve bit programming to the dcd boot-up tables. dcd is a table located in the start of the image that can hold up to 60 address/values. rom code reads addresses and writes va lues to it. this space should be sufficient to reprogram the nand flash pads for hve bits. 4.3.5 i 2 c i/o dc parameters note see the errata for hs-i2c in i.mx51 chip errata document. the two standard i 2 c modules have no errata. the dc electrical characteristics listed in table 22 are guaranteed using operating ranges per table 13 , unless otherwise noted. 4.3.6 usbotg electrical dc parameters this section describes the electrical dc parameters of usbotg. table 2 2. i 2 c standard/fast/high-speed mode electrical parameters for low/medium drive strength parameter symbol test conditions min typ max unit low-level output voltage vol iol = 3 ma ? ? 0.4 v high-level dc input voltage 1 1 to maintain a valid level, the transitioning edge of the input must sustain a constant slew rate (monotonic) from the current dc level through to the target dc level, vil or vih. monotonic input transition time is from 0.1 ns to 1 s. vih ? 0.7 ovdd ? ovdd v low-level dc input voltage 1 vil ? 0 ? 0.3 ovdd v input hysteresis vhys ? 0.25 ? ? v schmitt trigger vt+ 1,2 2 hysteresis of 250 mv is guaranteed over all operating conditions when hysteresis is enabled. vt+ ? 0.5 ovdd ? ? v schmitt trigger vt? 1,2 vt? ? ? ? 0.5 ovdd v i/o leakage current (no pull-up) iin vi = ovdd or 0 ? ? see note 3 3 i/o leakage currents are listed in ta b l e 2 5 . ?
i.mx51 applications processors for consumer and industrial products, rev. 6 30 freescale semiconductor electrical characteristics 4.3.7 usb port electrical dc characteristics table 23 and table 24 list the electrical dc characteristics. table 23. usbotg interface electrical specification parameter symbol signals min max unit test conditions input high voltage vih usb_vpout usb_vmout usb_xrxd, usb_vpin, usb_vmin vdd x 0.7 vdd v ? input low voltage vil usb_vpout usb_vmout usb_xrxd, usb_vpin, usb_vmin 0 vdd 0.3 v ? output high voltage voh usb_vpout usb_vmout usb_txenb vdd ? 0.43 ? v 7 ma drv at ioh = 5 ma output low voltage vol usb_vpout usb_vmout usb_txenb ?0 . 4 3v7 m a d r v at ioh = 5 ma table 24. usb interface electrical specification parameter symbol signals min max unit test conditions input high voltage vih usb_dat_vp usb_se0_vm usb_rcv, usb_vp1, usb_vm1 vdd x 0.7 vdd v ? input low voltage vil usb_dat_vp usb_se0_vm usb_rcv, usb_vp1, usb_vm1 0 vdd x 0.3 v ? output high voltage voh usb_dat_vp usb_se0_vm usb_txoe_b vdd ?0.43 ? v 7 ma drv at iout = 5 ma output low voltage vol usb_dat_vp usb_se0_vm usb_txoe_b ?0.43 v7 ma drv at iout = 5 ma
electrical characteristics i.mx51 applications processors for consumer and industrial products, rev. 6 freescale semiconductor 31 table 25 shows the i/o leakage currents that are based on the operating ranges in table 13 and the operating temperatures in table 1 . . 4.4 output buffer impedance characteristics this section defines the i/o impedance parameters of the i.mx51 processor. 4.4.1 lvio i/o output buffer impedance table 26 shows the lvio i/o output buffer impedance. table 25. i/o leakage current contact group supply rail test condition min typ max unit nandf nvcc_nandf v[i/o] = gnd or positive supply rail, i/o = high z ?? 1 a eim nvcc_emi v[i/o] = gnd or positive supply rail, i/o = high z ?? 1 a dram nvcc_dram v[i/o] = gnd or positive supply rail, i/o = high z ?? 2.5 a csi1, csi2, disp1_data[5:0] nvcc_hsx v[i/o] = gnd or positive supply rail, i/o = high z ?? 1.5 a i 2 c1 nvcc_i2c v[i/o] = gnd or positive supply rail, i/o = high z ?? 1 a di1_dat[23:6], dispb_ser_x, di_gpx nvcc_ipu v[i/o] = gnd or positive supply rail, i/o = high z ?? 2 a ckil, pmic_x nvcc_srtc_pow v[i/o] = gnd or positive supply rail, i/o = high z ?? 1 a extal, xtal nvcc_osc v[i/o] = gnd or positive supply rail, i/o = high z ? ? 170 a id, gpanaio nvcc_usbphy v[i/o] = gnd or positive supply rail, i/o = high z ? ? 170 a disp2_dat[0:15] nvcc_ipu, nvcc_hs v[i/o] = gnd or positive supply rail, i/o = high z ?? 2 a sd1, sd2 nvcc_per15, nvcc_per17 v[i/o] = gnd or positive supply rail, i/o = high z ?? 10 a peripherals except sd1, sd2 nvcc_perx v[i/o] = gnd or positive supply rail, i/o = high z ?? 2 a
i.mx51 applications processors for consumer and industrial products, rev. 6 32 freescale semiconductor electrical characteristics 4.4.2 ddr2 output buffer impedance table 27 shows the ddr2 output buffer impedance. table 26. lvio i/o output buffer impedance parameter symbol conditions min typical max unit ovdd 2.775 v ovdd 1.875 v output driver impedance rpu low drive strength, ztl = 150 medium drive strength, ztl = 75 high drive strength, ztl = 50 max drive strength, ztl = 37.5 80 40 27 20 104 52 35 26 150 75 51 38 250 125 83 62 output driver impedance rpd low drive strength, ztl = 150 medium drive strength, ztl = 75 high drive strength, ztl = 50 max drive strength, ztl = 37.5 64 32 21 16 88 44 30 22 134 66 44 34 243 122 81 61 table 27. ddr2 i/o output buffer impedance hve = 0 parameter symbol test conditions best case t j = ?40 c ovdd = 1.95 v vcc = 1.3 v typical t j = 25 c ovdd = 1.8 v vcc = 1.2 v worst case t j = 105 c ovdd = 1.6 v vcc = 1.1 v unit s0?s5 000000 s0?s5 101010 s0?s5 111111 output driver impedance rpu low drive strength, ztl = 150 medium drive strength, ztl = 75 high drive strength, ztl = 50 max drive strength 185 92.5 61.7 26.5 140 70 47 19.5 111.4 55.7 37.2 15.4 output driver impedance rpd low drive strength, ztl = 150 medium drive strength, ztl = 75 high drive strength, ztl = 50 max drive strength 190.3 95.1 63.4 27.6 145.4 72.7 48.5 19.9 120.6 60.3 40.2 16.9
electrical characteristics i.mx51 applications processors for consumer and industrial products, rev. 6 freescale semiconductor 33 4.4.3 uhvio output buffer impedance table 28 shows the uhvio output buffer impedance. note output driver impedance is measured with long transmission line of impedance ztl attached to i/o pad and incident wave launched into transmission lime. rpu/rpd and ztl form a voltage divider that defines specific voltage of incident wave relative to ovdd. output driver impedance is calculated from this voltage divider (see figure 3 ). table 28. uhvio output buffer impedance parameter symbol test conditions min typ max unit ovdd 1.95 v ovdd 3.0 v ovdd 1.875 v ovdd 3.3 v ovdd 1.65 v ovdd 3.6 v output driver impedance rpu low drive strength, ztl = 150 medium drive strength, ztl = 75 high drive strength, ztl = 50 98 49 32 114 57 38 124 62 41 135 67 45 198 99 66 206 103 69 output driver impedance rpd low drive strength, ztl =1 50 medium drive strength, ztl = 75 high drive strength, ztl = 50 97 49 32 118 59 40 126 63 42 154 77 51 179 89 60 217 109 72
i.mx51 applications processors for consumer and industrial products, rev. 6 34 freescale semiconductor electrical characteristics figure 3. impedance matching load for measurement ipp_do cload = 1p ztl , l = 20 inches predriver pmos (rpu) nmos (rpd) pad ovdd ovss t,(ns) 0 u,(v) ovdd t,(ns) 0 vdd vin (do) vout (pad) u,(v) vref rpu = vovdd ? vref1 vref1 ztl rpd = ztl vref2 vovdd ? vref2 vref1 vref2
electrical characteristics i.mx51 applications processors for consumer and industrial products, rev. 6 freescale semiconductor 35 4.5 i/o ac parameters the load circuit and output transition time waveforms are shown in figure 4 and figure 5 . ac electrical characteristics for slow and fast i/o are presented in the table 29 and table 30 , respectively. figure 4. load circuit for output figure 5. output transition time waveform 4.5.1 slow i/o ac parameters table 29 shows the slow i/o ac parameters. table 29. slow i/o ac parameters parameter symbol test condition min rise/fall typ max rise/fall unit output pad transition times (max drive) tr, tf 15 pf 35 pf ? ? 1.98/1.52 3.08/2.69 ns output pad transition times (high drive) tr, tf 15 pf 35 pf ? ? 2.31/1.838 3.8/2.4 ns output pad transition times (medium drive) tr, tf 15 pf 35 pf ? ? 2.92/2.43 5.37/4.99 ns output pad transition times (low drive) tr, tf 15 pf 35 pf ? ? 4.93/4.53 10.55/9.79 ns output pad slew rate (max drive) tps 15 pf 35 pf 0.5/0.65 0.32/0.37 ?? v/ns output pad slew rate (high drive) tps 15 pf 35 pf 0.43/0.54 0.26/0.41 ?? v/ns output pad slew rate (medium drive) tps 15 pf 35 pf 0.34/0.41 0.18/0.2 ?? v/ns output pad slew rate (low drive) tps 15 pf 35 pf 0.20/0.22 0.09/0.1 ?? v/ns output pad di/dt (max drive) tdit ? ? ? 30 ma/ns output pad di/dt (high drive) tdit ? ? ? 23 ma/ns output pad di/dt (medium drive) tdit ? ? ? 15 ma/ns tes t po in t from output under test cl cl includes package, probe and fixture capacitance 0v nvcc 20% 80% 80% 20% tr tf output (at i/o)
i.mx51 applications processors for consumer and industrial products, rev. 6 36 freescale semiconductor electrical characteristics 4.5.2 fast i/o ac parameters table 30 shows the fast i/o ac parameters. 4.5.3 i 2 c ac parameters note see the errata for hs-i 2 c in the i.mx51 chip errata document. the two standard i 2 c modules have no errata output pad di/dt (low drive) tdit ? ? ? 7 ma/ns input transition times 1 trm ? ? ? 25 ns 1 hysteresis mode is recommended for inputs with transition times greater than 25 ns. table 30. fast i/o ac parameters parameter symbol test condition min rise/fall typ max rise/fall unit output pad transition times (max drive) tr, tf 15 pf 35 pf ? ? 1.429/1.275 2.770/2.526 ns output pad transition times (high drive) tr, tf 15 pf 35 pf ? ? 1.793/1.607 3.565/3.29 ns output pad transition times (medium drive) tr, tf 15 pf 35 pf ? ? 2.542/2.257 5.252/4.918 ns output pad transition times (low drive) tr, tf 15 pf 35 pf ? ? 4.641/4.456 10.699/10.0 ns output pad slew rate (max drive) tps 15 pf 35 pf 0.69/0.78 0.36/0.39 ?? v / n s output pad slew rate (high drive) tps 15 pf 35 pf 0.55/0.62 0.28/0.30 ?? v / n s output pad slew rate (medium drive) tps 15 pf 35 pf 0.39/0.44 0.19/0.20 ?? v / n s output pad slew rate (low drive) tps 15 pf 35 pf 0.21/0.22 0.09/0.1 ?? v / n s output pad di/dt (max drive) tdit ? ? ? 70 ma/ns output pad di/dt (high drive) tdit ? ? ? 53 ma/ns output pad di/dt (medium drive) tdit ? ? ? 35 ma/ns output pad di/dt (low drive) tdit ? ? ? 18 ma/ns input transition times 1 1 hysteresis mode is recommended for inputs with transition time greater than 25 ns. trm ? ? ? 25 ns table 29. slow i/o ac parameters (continued) parameter symbol test condition min rise/fall typ max rise/fall unit
electrical characteristics i.mx51 applications processors for consumer and industrial products, rev. 6 freescale semiconductor 37 figure 6 depicts the load circuit for output pads for standard- and fast-mode. figure 7 depicts the output pad transition time definition. figure 8 depicts load circuit with external pull-up current source for hs-mode. figure 9 depicts hs-mode timing definition. figure 6. load circuit for standard and fast-mode figure 7. definition of timing for standard and fast-mode figure 8. load circuit for hs-mode with external pull-up current source figure 9. definition of timing for hs-mode te st po in t from output under test cl cl includes package, probe and fixture capacitance 0v ovdd 70% 30% tf output te st po in t from output under test cl 2 3 ma 1 ovdd 1 load current when output is between 0.3 ovdd and 0.7 ovdd 2 cl includes package, probe, and fixture capacitance. notes: 0v ovdd 30% 70% 70% 30% t tlh t thl output (at pad) pa3max = max of t tlh and t thl pa4max = max t thl
i.mx51 applications processors for consumer and industrial products, rev. 6 38 freescale semiconductor electrical characteristics the electrical characteristics for i 2 c i/o are listed in table 31 to table 34 . characteristics are guaranteed using operating ranges per table 13 , unless otherwise noted. table 31. i 2 c standard- and fast-mode electrical parameters for low/medium drive strength and ovdd = 2.7 v?3.3 v parameter symbol test conditions min typ max unit output fall time, (low driver strength) tf from v ihmin to v ilmax with c l from 10 pf to 400 pf ? ? 52 ns output fall time, (medium driver strength) tf from v ihmin to v ilmax with c l from 10 pf to 400 pf ? ? 28 ns table 32. i 2 c standard- and fast-mode electrical parameters for low/medium drive strength and ovdd = 1.65 v?1.95 v parameter symbol test conditions min typ max unit output fall time, (low driver strength) t of from v ihmin to v ilmax with c l from 10 pf to 400 pf ? ? 70 ns output fall time, (medium driver strength) t of from v ihmin to v ilmax with c l from 10 pf to 400 pf ? ? 35 ns table 33. i 2 c high-speed mode electrical parameters for low/medium drive strength and ovdd = 2.7 v?3.3 v parameter symbol test conditions min typ max unit output rise time (current-source enabled) and fall time at sclh (low driver strength) t rcl , t fcl with a 3ma external pull-up current source and c l = 100 pf ? ? 18/21 ns output rise time (current-source enabled) and fall time at sclh (medium driver strength) t rcl , t fcl with a 3ma external pull-up current source and c l = 100 pf ?? 9/9 ns output fall time at sdah (low driver strength) t fda with c l from 10 pf to 100 pf ? ? 14 ns output fall time at sdah (medium driver strength) t fda with c l from 10 pf to 100 pf ?? 8 ns output fall time at sdah (low driver strength) t fda c l = 400 pf ? ? 52 ns output fall time at sdah (medium driver strength) t fda c l = 400 pf ? ? 27 ns
electrical characteristics i.mx51 applications processors for consumer and industrial products, rev. 6 freescale semiconductor 39 table 34. i 2 c high-speed mode electrical parameters for low/medium drive strength and ovdd = 1.65 v?1.95 v parameter symbol test conditions min typ max unit output rise time (current-source enabled) and fall time at sclh (low driver strength) t rcl , t fcl with a 3 ma external pull-up current source and c l = 100 pf ??10/74ns output rise time (current-source enabled) and fall time at sclh (medium driver strength) t rcl , t fcl with a 3 ma external pull-up current source and c l = 100 pf ? ? 7/14 ns output fall time at sdah (low driver strength) t fda with c l from 10 pf to 100 pf 0 ? 17 ns output fall time at sdah (medium driver strength) t fda with c l from 10 pf to 100 pf 0 ? 9 ns output fall time at sdah (low driver strength) t fda c l = 400 pf 30 ? 67 ns output fall time at sdah (medium driver strength) t fda c l = 400 pf 15 ? 34 ns table 35. low voltage i 2 c i/o parameters parameter symbol test condition min rise/fall typ max rise/fall unit output pad di/dt (medium drive) tdit ? ? ? 22 ma/ns output pad di/dt (low drive) tdit ? ? ? 11 ma/ns input transition times 1 1 hysteresis mode is recommended for inputs with transition time greater than 25 ns trm ? ? ? 25 ns table 36. high voltage i 2 c i/o parameters parameter symbol test condition min rise/fall typ max rise/fall unit output pad transition times (medium drive) tr, tf 15 pf 35 pf ?? 3/3 6/5 ns output pad transition times (low drive) tr, tf 15 pf 35 pf ?? 5/5 9/9 ns output pad slew rate (medium drive) tps 15 pf 35 pf 0/0 0/0 ??v / n s output pad slew rate (low drive) tps 15 pf 35 pf 0/0 0/0 ??v / n s output pad di/dt (medium drive) tdit ? ? ? 36 ma/ns output pad di/dt (low drive) tdit ? ? ? 16 ma/ns input transition times 1 1 hysteresis mode is recommended for inputs with transition time > 25 ns trm ? ? ? 25 ns
i.mx51 applications processors for consumer and industrial products, rev. 6 40 freescale semiconductor electrical characteristics 4.5.4 ac electrical characteristics for ddr2 the load circuit for output pads, the output pad transition time waveform and the output pad propagation and transition time waveform are below. figure 10 shows the output pad transition time waveform. figure 10. output pad transition time waveform figure 11 shows the output pad propagation and transition time waveform. figure 11. output pad propagation and transition time waveform ac electrical characteristics in ddr2 mode for fast mode and for ovdd = 1.65 ? 1.95 v, ipp_hve = 0 are placed in table 37 . table 37. ac electrical characteristics of ddr2 io pads for fast mode and for ovdd=1.65?1.95 v (ipp_hve=0) parameter symbol test condition min rise/fall typ max rise/fall units output pad transition times 1 tpr 15pf 35pf 0.57/0.57 1.29/1.29 0.45/0.44 0.97/0.94 0.45/0.45 0.82/0.85 ns output pad propagation delay, 50%-50% 1 tpo 15pf 35pf 0.98/0.96 1.47/1.50 1.27/1.19 1.63/1.57 1.89/1.72 2.20/2.07 ns output pad slew rate 1 tps 15pf 35pf 2.05/2.05 0.91/0.91 2.40/2.45 1.11/1.15 2.20/2.20 1.21/1.16 v/ns
electrical characteristics i.mx51 applications processors for consumer and industrial products, rev. 6 freescale semiconductor 41 ac electrical characteristics in ddr2 mode for slow mode and for ovdd=1.65 ? 1.95 v, ipp_hve = 0 are placed in table 38 : output pad di/dt 1 di/dt ? 390 201 99 ma/ns input pad transition times 2 trfi 1.2 pf 0.09/0.09 0.132/0.128 0.212/0.213 ns input pad propagation delay without hysteresis (cmos input), 50%-50% 2 tpi 1.2 pf 0.45/0.93 0.6/0.58 0.9/0.88 ns input pad propagation delay with hysteresis (cmos input), 50%-50% 2 tpi 1.2 pf 0.55/0.55 0.71/0.7 1.03/0.98 ns input pad propagation delay (ddr input), 50%-50% 2 tpi 1.2 pf 0.38/0.38 0.58/0.61 1.014/1.07 ns maximum input transition times 3 trm ? ? ? 5 ns 1 max condition for tpr, tpo, tps and didt: wcs model, 1.1 v, io 1.65 v, 105 c and s0-s5=111111. typ condition for tpr, tpo, tps and didt: typ model, 1.2 v, io 1.8 v, 25 c and s0-s5 = 101010. min condition for tpr, tpo, tps and didt: bcs model, 1.3 v, io 1.95 v, ?40 c and s0-s5=000000. 2 max condition for trfi and tpi: wcs model, 1.1 v, io 1.65 v and 105 c. typ condition for trfi and tpi: typ model, 1.2 v, io 1.8 v and 25 c. min condition for trfi and tpi: bcs model, 1.3 v, io 1.95 v and ?40 c. 3 hysteresis mode is recommended for input with transition time greater than 25 ns. table 38. ac electrical characteristics of ddr2 io pads for slow mode and for ovdd=1.65?1.95 v (ipp_hve=0) parameter symbol test condition min rise/fall typ max rise/fall units output pad transition times 1 tpr 15pf 35pf 0.75/0.76 1.39/1.40 0.70/0.74 1.18/1.21 1.06/1.00 1.49/1.47 ns output pad propagation delay, 50%-50% 1 tpo 15pf 35pf 1.50/1.55 2.05/2.16 1.90/1.95 2.36/2.48 3.23/3.10 3.82/3.75 ns output pad slew rate 1 tps 15pf 35pf 1.56/1.54 0.84/0.84 1.54/1.46 0.92/0.89 0.93/0.99 0.66/0.67 v/ns output pad di/dt 1 di/dt ? 82 40 19 ma/ns input pad transition times 2 trfi 1.2 pf 0.09/0.09 0.132/0.128 0.212/0.213 ns input pad propagation delay without hysteresis (cmos input), 50%-50% 2 tpi 1.2 pf 0.45/0.93 0.6/0.58 0.9/0.88 ns input pad propagation delay with hysteresis (cmos input), 50%-50% 2 tpi 1.2 pf 0.55/0.55 0.71/0.7 1.03/0.98 ns input pad propagation delay (ddr input), 50%-50% 2 tpi 1.2 pf 0.38/0.38 0.58/0.61 1.014/1.07 ns maximum input transition times 3 trm ? ? ? 5 ns table 37. ac electrical characteristics of ddr2 io pads for fast mode and for ovdd=1.65?1.95 v (ipp_hve=0) (continued) parameter symbol test condition min rise/fall typ max rise/fall units
i.mx51 applications processors for consumer and industrial products, rev. 6 42 freescale semiconductor electrical characteristics ac electrical characteristics in ddr mobile for fa st mode and ovdd=1.65 ? 1.95 v, ipp_hve=0 are placed in table 39 . 1 max condition for tpr, tpo, tps and didt: wcs model, 1.1 v, io 1.65 v, 105 c and s0-s5=111111. typ condition for tpr, tpo, tps and didt: typ model, 1.2 v, io 1.8 v, 25 c and s0-s5 = 101010. min condition for tpr, tpo, tps and didt: bcs model, 1.3 v, io 1.95 v, ?40 c and s0-s5 = 000000. 2 max condition for trfi and tpi: wcs model, 1.1 v, io 1.65 v and 105 c. typ condition for trfi and tpi: typ model, 1.2 v, io 1.8 v and 25 c. min condition for trfi and tpi: bcs model, 1.3 v, io 1.95 v and ?40 c. 3 hysteresis mode is recommended for input with transition time greater than 25 ns. table 39. ac electrical characteristics of ddr mobile io pads for fast mode and ovdd=1.65?1.95 v (ipp_hve=0) parameter symbol test condition min rise/fall typ max rise/fall units output pad transition times (high drive) 1 tpr 15pf 35pf 1.35/1.31 2.99/2.94 1.02/1.03 2.28/2.29 0.89/0.89 1.85/1.94 ns output pad transition times (medium drive) 1 tpr 15pf 35pf 2.00/1.99 4.55/4.44 1.56/1.53 3.38/3.45 1.28/1.32 2.79/2.85 ns output pad transition times (low drive) 1 tpr 15pf 35pf 4.08/3.92 8.93/8.95 3.11/3.06 6.84/6.81 2.50/2.61 5.56/5.76 ns output pad propagation delay (high drive) 1 tpo 15pf 35pf 1.54/1.52 2.69/2.75 1.73/1.62 2.59/2.55 2.36/2.09 3.04/2.86 ns output pad propagation delay (medium drive) 1 tpo 15pf 35pf 2.00/2.02 3.75/3.86 2.08/2.00 3.38/3.39 2.64/2.40 3.65/3.56 ns output pad propagation delay (low drive) 1 tpo 15pf 35pf 3.43/3.52 6.92/7.20 3.13/3.13 5.72/5.94 3.47/3.34 5.49/5.65 ns output pad slew rate (high drive) 1 tps 15pf 35pf 0.87/0.89 0.39/0.40 1.06/1.05 0.47/0.47 1.11/1.11 0.54/0.51 v/ns output pad slew rate (medium drive) 1 tps 15pf 35pf 0.58/0.59 0.26/0.26 0.69/0.71 0.32/0.31 0.77/0.75 0.35/0.35 v/ns output pad slew rate (low drive) 1 tps 15pf 35pf 0.29/0.30 0.13/0.13 0.35/0.35 0.16/0.16 0.40/0.38 0.18/0.17 v/ns output pad di/dt (high drive) 1 di/dt ? 185 91 46 ma/ns output pad di/dt (medium drive) 1 di/dt ? 124 61 31 ma/ns output pad di/dt (low drive) 1 di/dt ? 62 30 16 ma/ns input pad transition times 2 trfi 1.2 pf 0.09/0.09 0.132/0.128 0.212/0.213 ns input pad propagation delay without hysteresis (cmos input), 50%-50% 2 tpi 1.2 pf 0.45/0.93 0.6/0.58 0.9/0.88 ns input pad propagation delay with hysteresis (cmos input), 50%-50% 2 tpi 1.2 pf 0.55/0.55 0.71/0.7 1.03/0.98 ns input pad propagation delay (ddr input), 50%-50% 2 tpi 1.2 pf 0.38/0.38 0.58/0.61 1.014/1.07 ? maximum input transition times 3 trm ? ? ? 5 ns
electrical characteristics i.mx51 applications processors for consumer and industrial products, rev. 6 freescale semiconductor 43 ac electrical characteristics in ddr mobile for slow mode and ovdd=1.65-1.95v, ipp_hve=0 are placed in table 40 . 1 max condition for tpr, tpo, tps and didt: wcs model, 1.1 v, io 1.65 v, 105 c and s0-s5=111111. typ condition for tpr, tpo, tps and didt: typ model, 1.2 v, io 1.8 v, 25 c and s0-s5 = 101010. min condition for tpr, tpo, tps and didt: bcs model, 1.3 v, io 1.95 v, ?40 c and s0-s5 = 000000. 2 max condition for trfi and tpi: wcs model, 1.1 v, io 1.65 v and 105 c. typ condition for trfi and tpi: typ model, 1.2 v, io 1.8 v and 25 c. min condition for trfi and tpi: bcs model, 1.3 v, io 1.95 v and ?40 c. 3 hysteresis mode is recommended for input with transition time greater than 25 ns. table 40. ac electrical characteristics of ddr mobile io pads for slow mode ovdd=1.65?1.95 v (ipp_hve=0) parameter symbol test condition min rise/fall typ max rise/fall units output pad transition times (high drive) 1 tpr 15pf 35pf 1.42/1.43 3.03/2.92 1.20/1.27 2.39/2.38 1.43/1.49 2.35/2.46 ns output pad transition times (medium drive) 1 tpr 15pf 35pf 2.04/2.04 4.51/4.49 1.68/1.74 3.47/3.50 1.82/1.91 3.16/3.30 ns output pad transition times (low drive) 1 tpr 15pf 35pf 4.08/3.93 9.06/8.93 3.16/3.19 6.92/6.93 2.90/3.01 5.74/5.96 ns output pad propagation delay (high drive) 1 tpo 15pf 35pf 2.00/2.17 3.15/3.42 2.33/2.50 3.24/3.52 3.70/3.70 4.63/4.75 ns output pad propagation delay (medium drive) 1 tpo 15pf 35pf 2.47/2.68 4.2/4.53 2.72/2.92 4.01/4.37 4.10/4.16 5.33/5.55 ns output pad propagation delay (low drive) 1 tpo 15pf 35pf 3.87/4.18 7.32/7.86 3.78/4.10 6.35/6.90 5.13/5.30 7.25/7.73 ns output pad slew rate (high drive) 1 tps 15pf 35pf 0.82/0.82 0.39/0.40 0.90/0.85 0.45/0.49 0.69/0.66 0.42/0.40 v/ns output pad slew rate (medium drive) 1 tps 15pf 35pf 0.57/0.57 0.26/0.26 0.70/0.62 0.31/0.31 0.54/0.52 0.31/0.30 v/ns output pad slew rate (low drive) 1 tps 15pf 35pf 0.29/0.30 0.13/0.13 0.34/0.34 0.16/0.16 0.34/0.33 0.17/0.17 v/ns output pad di/dt (high drive) 1 di/dt 47 14 9 ma/ns output pad di/dt (medium drive) 1 di/dt ? 27 9 6 ma/ns output pad di/dt (low drive) 1 di/dt ? 12 5 3 ma/ns input pad transition times 2 trfi 1.2 pf 0.09/0.09 0.132/0.128 0.212/0.213 ns input pad propagation delay without hysteresis (cmos input), 50%-50% 2 tpi 1.2 pf 0.45/0.93 0.6/0.58 0.9/0.88 ns input pad propagation delay with hysteresis (cmos input), 50%-50% 2 tpi 1.2 pf 0.55/0.55 0.71/0.7 1.03/0.98 ns input pad propagation delay (ddr input), 50%-50% 2 tpi 1.2 pf 0.38/0.38 0.58/0.61 1.014/1.07 ? maximum input transition times 3 trm ? ? ? 5 ns
i.mx51 applications processors for consumer and industrial products, rev. 6 44 freescale semiconductor electrical characteristics ac electrical characteristics in ddr2 mode for fast mode and for ovdd=1.65?1.95v, ipp_hve=0 are placed in table 41 . ac electrical characteristics in ddr2 mode for slow mode and for ovdd=1.65-1.95v, ipp_hve=0 are placed in table 42 . 1 max condition for tpr, tpo, tps and didt: wcs model, 1.1 v, io 1.65 v, 105 c and s0-s5=111111. typ condition for tpr, tpo, tps and didt: typ model, 1.2 v, io 1.8 v, 25 c and s0-s5=101010. min condition for tpr, tpo, tps and didt: bcs model, 1.3 v, io 1.95 v, ?40 c and s0-s5=000000. 2 max condition for trfi and tpi: wcs model, 1.1 v, io 1.65 v and 105 c. typ condition for trfi and tpi: typ model, 1.2 v, io 1.8 v and 25 c. min condition for trfi and tpi: bcs model, 1.3 v, io 1.95 v and ?40 c. 3 hysteresis mode is recommended for input with transition time greater than 25 ns. table 41. ac electrical characteristics of ddr2_clk io pads for fast mode and for ovdd=1.65?1.95 v parameter symbol test condition min rise/fall typ max rise/fall units output pad transition times 1 1 max condition for tpr, tpo, tps and didt: wcs model, 1.1 v, io 1.65 v, 105 c and s0-s5=111111. typ condition for tpr, tpo, tps and didt: typ model, 1.2 v, io 1.8 v, 25 c and s0-s5=101010. min condition for tpr, tpo, tps and didt: bcs model, 1.3 v, io 1.95 v, -40 c and s0-s5=000000. tpr 15pf 35pf 0.58/0.57 1.29/1.28 0.45/0.44 0.97/0.93 0.45/0.45 0.82/0.85 ns output pad propagation delay, 50%-50% 1 tpo 15pf 35pf 1.05/1.03 1.54/1.56 1.40/1.31 1.75/1.69 2.12/1.96 2.43/2.31 ns output pad slew rate 1 tps 15pf 35pf 2.02/2.05 0.91/0.91 2.40/2.45 1.11/1.16 2.20/2.20 1.21/1.16 v/ns output pad di/dt 1 di/dt ? 390 201 99 ma/ns input pad transition times 2 2 max condition for trfi and tpi: wcs model, 1.1 v, io 1.65 v and 105 c. typ condition for trfi and tpi: typ model, 1.2 v, io 1. 8 v and 25 c. min condition for trfi and tpi: bcs model, 1.3 v, io 1.95 v and -40 c. trfi 1.2 pf 0.09/0.09 0.132/0.128 0.212/0.213 ns input pad propagation delay (ddr input), 50%-50% 2 tpi 1.2 pf 0.3/0.36 0.5/0.52 0.82/0.94 ns maximum input transition times 3 3 hysteresis mode is recommended for input with transition time greater than 25 ns. trm ? ? ? 5 ns table 42. ac electrical characteristics of ddr2_clk io pads for slow mode and for ovdd=1.65 ? 1.95 v (ipp_hve=0) parameter symbol test condition min rise/fall typ max rise/fall units output pad transition times 1 tpr 15pf 35pf 0.74/0.76 1.40/1.39 0.69/0.72 1.18/1.20 1.04/1.01 1.48/1.47 ns output pad propagation delay, 50%-50% 1 tpo 15pf 35pf 1.56/1.61 2.12/2.22 2.02/2.08 2.49/2.61 3.45/3.33 4.05/3.98 ns output pad slew rate 1 tps 15pf 35pf 1.58/1.54 0.84/0.84 1.57/1.50 0.92/0.90 0.95/0.98 0.67/0.67 v/ns
electrical characteristics i.mx51 applications processors for consumer and industrial products, rev. 6 freescale semiconductor 45 ac electrical characteristics in ddr mobile for fa st mode and ovdd=1.65-1.95v, ipp_hve=0 are placed in table 43 . output pad di/dt 1 di/dt ? 82 40 19 ma/ns input pad transition times 2 trfi 1.2 pf 0.09/0.09 0.132/0.128 0.212/0.213 ns input pad propagation delay (ddr input), 50%-50% 2 tpi 1.2 pf 0.3/0.36 0.5/0.52 0.82/0.94 ns maximum input transition times 3 trm ? ? ? 5 ns 1 max condition for tpr, tpo, tps and didt: wcs model, 1.1 v, io 1.65 v, 105 c and s0-s5=111111. typ condition for tpr, tpo, tps and didt: typ model, 1.2 v, io 1.8 v, 25 c and s0-s5=101010. min condition for tpr, tpo, tps and didt: bcs model, 1.3 v, io 1.95 v, -40 c and s0-s5=000000. 2 max condition for trfi and tpi: wcs model, 1.1 v, io 1.65 v and 105 c. typ condition for trfi and tpi: typ model, 1.2 v, io 1. 8 v and 25 c. min condition for trfi and tpi: bcs model, 1.3 v, io 1.95 v and -40 c. 3 hysteresis mode is recommended for input with transition time greater than 25 ns. table 43. ac electrical characteristics of ddr_clk mobile io pads for fast mode and ovdd=1.65 ? 1.95 v (ipp_hve=0) parameter symbol test condition min rise/fall typ max rise/fall units output pad transition times (high drive) 1 tpr 15pf 35pf 1.35/1.32 3.01/2.96 1.03/1.03 2.29/2.30 0.89/0.89 1.84/1.92 ns output pad transition times (medium drive) 1 tpr 15pf 35pf 1.98/1.98 4.52/4.38 1.55/1.54 3.46/3.45 1.29/1.30 2.80/2.88 ns output pad transition times (low drive) 1 tpr 15pf 35pf 3.99/3.94 8.93/8.86 3.10/3.04 6.77/6.85 2.50/2.57 5.40/5.68 ns output pad propagation delay (high drive) 1 tpo 15pf 35pf 1.60/1.58 2.74/2.81 1.85/1.74 2.71/2.67 2.58/2.31 3.26/3.08 ns output pad propagation delay (medium drive) 1 tpo 15pf 35pf 2.07/2.08 3.79/3.92 2.19/2.12 3.46/3.51 2.86/2.62 3.87/3.77 ns output pad propagation delay (low drive) 1 tpo 15pf 35pf 3.47/3.57 6.94/7.26 3.23/3.25 5.84/6.06 3.69/3.55 5.73/5.87 ns output pad slew rate (high drive) 1 tps 15pf 35pf 0.87/0.89 0.39/0.40 1.05/1.05 0.47/0.47 1.11/1.11 0.54/0.52 v/ns output pad slew rate (medium drive) 1 tps 15pf 35pf 0.59/0.59 0.26/0.27 0.70/0.70 0.31/0.31 0.77/0.76 0.35/0.34 v/ns output pad slew rate (low drive) 1 tps 15pf 35pf 0.29/0.30 0.13/0.13 0.35/0.36 0.16/0.16 0.40/0.39 0.18/0.17 v/ns output pad di/dt (high drive) 1 di/dt ? 185 91 46 ma/ns output pad di/dt (medium drive) 1 di/dt ? 124 61 31 ma/ns table 42. ac electrical characteristics of ddr2_clk io pads for slow mode and for ovdd=1.65 ? 1.95 v (ipp_hve=0) (continued) parameter symbol test condition min rise/fall typ max rise/fall units
i.mx51 applications processors for consumer and industrial products, rev. 6 46 freescale semiconductor electrical characteristics ac electrical characteristics in ddr mobile for slow mode and ovdd=1.65-1.95v, ipp_hve=0 are placed in table 44 . output pad di/dt (low drive) 1 di/dt ? 62 30 16 ma/ns input pad transition times 2 trfi 1.2 pf 0.09/0.09 0.132/0.128 0.212/0.213 ns input pad propagation delay (ddr input), 50%-50% 2 tpi 1.2 pf 0.3/0.36 0.5/0.52 0.82/0.94 ? maximum input transition times 3 trm ? ? ? 5 ns 1 max condition for tpr, tpo, tps and didt: wcs model, 1.1 v, io 1.65 v, 105 c and s0-s5=111111. typ condition for tpr, tpo, tps and didt: typ model, 1.2 v, io 1.8 v, 25 c and s0-s5=101010. min condition for tpr, tpo, tps and didt: bcs model, 1.3 v, io 1.95 v, ?40 c and s0-s5=000000. 2 max condition for trfi and tpi: wcs model, 1.1 v, io 1.65 v and 105 c. typ condition for trfi and tpi: typ model, 1.2 v, io 1.8 v and 25 c. min condition for trfi and tpi: bcs model, 1.3 v, io 1.95 v and ?40 c. 3 hysteresis mode is recommended for input with transition time greater than 25 ns. table 44. ac electrical characteristics of ddr mobile io pads for slow mode and ovdd=1.65 ? 1.95 v (ipp_hve=0) parameter symbol test condition min rise/fall typ max rise/fall units output pad transition times (high drive) 1 tpr 15pf 35pf 1.42/1.42 3.01/2.96 1.20/1.27 2.38/2.40 1.43/1.49 2.37/2.44 ns output pad transition times (medium drive) 1 tpr 15pf 35pf 2.05/2.04 4.50/4.42 1.67/1.71 3.48/3.52 1.82/1.87 3.16/3.28 ns output pad transition times (low drive) 1 tpr 15pf 35pf 4.06/3.98 8.94/8.86 3.15/3.17 6.92/6.93 2.92/ 3.02 5.69/5.96 ns output pad propagation delay (high drive) 1 tpo 15pf 35pf 2.07/2.23 3.21/3.48 2.46/2.62 3.35/3.63 3.92/3.93 4.84/4.97 ns output pad propagation delay (medium drive) 1 tpo 15pf 35pf 2.53/2.74 4.26/4.58 2.83/3.04 4.12/4.49 4.32/4.35 5.55/5.76 ns output pad propagation delay (low drive) 1 tpo 15pf 35pf 3.93/4.23 7.38/7.91 3.89/4.21 6.43/7.01 5.37/5.51 7.45/7.94 ns output pad slew rate (high drive) 1 tps 15pf 35pf 0.82/0.82 0.39/0.40 0.90/0.85 0.45/0.45 0.69/0.66 0.42/0.41 v/ns output pad slew rate (medium drive) 1 tps 15pf 35pf 0.57/0.57 0.26/0.26 0.65/0.63 0.31/0.31 0.54/0.53 0.31/0.30 v/ns output pad slew rate (low drive) 1 tps 15pf 35pf 0.29/0.29 0.13/0.13 0.34/0.34 0.16/0.16 0.34/0.33 0.17/0.17 v/ns output pad di/dt (high drive) 1 di/dt ? 47 14 9 ma/ns output pad di/dt (medium drive) 1 di/dt ? 27 9 6 ma/ns table 43. ac electrical characteristics of ddr_clk mobile io pads for fast mode and ovdd=1.65 ? 1.95 v (ipp_hve=0) (continued) parameter symbol test condition min rise/fall typ max rise/fall units
electrical characteristics i.mx51 applications processors for consumer and industrial products, rev. 6 freescale semiconductor 47 4.6 module timing this section contains the timing and electrical pa rameters for the modules in the i.mx51 processor. 4.6.1 reset timings parameters figure 12 shows the reset timing and table 45 lists the timing parameters. figure 12. reset timing diagram output pad di/dt (low drive) 1 di/dt ? 12 5 3 ma/ns input pad transition times 2 trfi 1.2 pf 0.09/0.09 0.132/0.128 0.212/0.213 ns input pad propagation delay (ddr input), 50%-50% 2 tpi 1.2 pf 0.3/0.36 0.5/0.52 0.82/0.94 ? maximum input transition times 3 trm ? ? ? 5 ns 1 max condition for tpr, tpo, tps and didt: wcs model, 1.1 v, io 1.65 v, 105 c and s0-s5=111111. typ condition for tpr, tpo, tps and didt: typ model, 1.2 v, io 1.8 v, 25 c and s0-s5=101010. min condition for tpr, tpo, tps and didt: bcs model, 1.3 v, io 1.95 v, ?40 c and s0-s5=000000. 2 max condition for trfi and tpi: wcs model, 1.1 v, io 1.65 v and 105 c. typ condition for trfi and tpi: typ model, 1.2 v, io 1.8 v and 25 c. min condition for trfi and tpi: bcs model, 1.3 v, io 1.95 v and ?40 c. 3 hysteresis mode is recommended for input with transition time greater than 25 ns. table 45. reset timing parameters id parameter min max unit cc1 duration of reset_in to be qualified as valid (input slope = 5 ns) 50 ? ns table 44. ac electrical characteristics of ddr mobile io pads for slow mode and ovdd=1.65 ? 1.95 v (ipp_hve=0) (continued) parameter symbol test condition min rise/fall typ max rise/fall units reset_in cc1 (input)
i.mx51 applications processors for consumer and industrial products, rev. 6 48 freescale semiconductor electrical characteristics 4.6.2 wdog reset timing parameters figure 13 shows the wdog reset timing and table 46 lists the timing parameters. figure 13. watchdog_rst timing diagram note ckil is approximately 32 khz. t ckil is one period or approximately 30 s. 4.6.3 audmux timing parameters the audmux provides a programmable interconnect l ogic for voice, audio and data routing between internal serial interfaces (ssis) and external serial interfaces (audio and voice codecs). the ac timing of audmux external pins is hence governed by the ssi module. 4.6.4 clock amplifier parameters (ckih1, ckih2) the input to clock amplifier (camp) is internally ac-coupled allowing direct interface to a square wave or sinusoidal frequency source. no external series capacitors are required. table 47 shows the camp electrical parameters. table 46. watchdog_rst timing parameters id parameter min max unit cc5 duration of watchdog_reset assertion 1 ? t ckil table 47. camp electrical parameters (ckih1, ckih2) parameter min typ max unit input frequency 8.0 ? 40.0 mhz vil (for square wave input) 0 ? 0.3 v vih (for square wave input) nvcc_per3 - 0.25 ? nvcc_per3 v sinusoidal input amplitude 0.4 ? vdd vp-p output duty cycle 45 50 55 % watchdog_rst cc5 (input)
electrical characteristics i.mx51 applications processors for consumer and industrial products, rev. 6 freescale semiconductor 49 4.6.5 dpll electrical parameters table 48 shows the dpll electrical parameters. 4.6.6 nand flash controller (nfc) parameters this section provides the relative timing requirements among different signals of nfc at the module level in the different operational modes. timing parameters in figure 14 , figure 15 , figure 16 , figure 17 , figure 19 , and table 50 show the default nfc mode (asymmetric mode) using two flash cloc k cycles per one access of re_b and we_b. timing parameters in figure 14 , figure 15 , figure 16 , figure 18 , figure 19 , and table 50 show symmetric nfc mode using one flash clock cycle per one access of re_b and we_b. table 48. dpll electrical parameters parameter test conditions/remarks min typ max unit reference clock frequency range 1 1 device input range cannot exceed the electrical specifications of the camp, see ta ble 4 7 . ? 10 ? 100 mhz reference clock frequency range after pre-divider ?10?40mhz output clock frequency range (dpdck_2) ? 300 ? 1025 mhz pre-division factor 2 2 the values specified here are internal to dpll. inside the dpll, a ?1? is added to the value specified by the user.therefore, the user has to enter a value ?1? less than the desired value at the inputs of dpll for pdf and mfd. ?1 ? 1 6 ? multiplication factor integer part ? 5 ? 15 ? multiplication factor numerator 3 3 the maximum total multiplication factor (mfi + mfn/mfd) allowed is 15.therefore, if the mfi value is 15, mfn value must be zero. should be less than denominator ?67108862 ? 67108862 ? multiplication factor denominator 2 ? 1 ? 67108863 ? output duty cycle ? 48.5 50 51.5 % frequency lock time 4 (fol mode or non-integer mf) 4 t dpdref is the time period of the reference clock after predivider.according to the specification, the maximum lock time in fol mode is 398 cycles of divided reference clock when dpll starts after full reset. ???398 t d pdref phase lock time ? ? ? 100 s frequency jitter 5 (peak value) 5 tdck is the time period of the output clock, dpdck_2. ? ? 0.02 0.04 t dck phase jitter (peak value) fpl mode, integer and fractional mf ? 2.0 3.5 ns power dissipation f dck = 300 mhz @ avdd = 1.8 v, dvdd = 1.2 v f dck = 650 mhz @ avdd = 1.8 v, dvdd = 1.2 v ? ? 0.65 (avdd) 0.92 (dvdd) 1.98 (avdd) 1.8 (dvdd) mw
i.mx51 applications processors for consumer and industrial products, rev. 6 50 freescale semiconductor electrical characteristics with reference to the timing diagrams, a high is defined as 80% of signal value and low is defined as 20% of signal value. all parameters are given in nanoseconds. the bga contact load used in calculations is 20 pf (except for nf16 - 40 pf) and there is max drive strength on all contacts. all timing parameters are a function of t, which is th e period of the flash_clk clock (?enfc_clk? at system level). this clock frequency can be controlled by the user, configuring ccm (soc clock controller). the clock is derived from emi_slow_clk after single divider. table 49 demonstrates few examples for clock frequency settings. note a potential limitation for minimum clock frequency may exist for some devices. when the clock frequency is too low the actual data bus capturing might occur after the specified trhoh (re_b high to output hold) period. setting the clock frequency above 25.6 m hz (t = 39 ns) guarantees proper operation for devices having trhoh > 15 ns. it is also recommended to set the nfc_freq_sel fuse accordingly to initiate the boot with 33.33 mhz clock. lower frequency operation can be supported for most available devices in the market, relying on data lines bus-keeper logic. this depends on device behavior on the data bus in the time in terval between data output valid to data output high-z state. in nand devi ce parameters this period is marked between trhoh and trhz (re_b high to output high-z). in most devices, the data transition from valid value to high-z occurs without going through other states. setting the data bus pads to bus-keeper mode in the iomux registers, keeps the data bus valid internally after the specified hold time, allowing proper capturing with slower clock. table 49. nfc clock settings examples emi_slow_clk (mhz) nfc_podf (division factor) enfc_clk (mhz) t?clock period (ns) 1 1 rounded up to whole nanoseconds. 133 (max value) 5 (reset value) 26.6 38 133 4 33.25 31 133 3 44.33 23
electrical characteristics i.mx51 applications processors for consumer and industrial products, rev. 6 freescale semiconductor 51 figure 14. command latch cycle timing figure 15. address latch cycle timing figure 16. write data latch timing nfcle nfce_b nfwe_b nfio[7:0] command nf9 nf8 nf1 nf2 nf5 nf3 nf4 nfce_b nfwe_b nfale nfio[7:0] address nf9 nf8 nf5 nf3 nf4 nf6 nf11 nf10 nf7 nfce_b nfwe_b nfio[15:0] data to nf nf9 nf8 nf5 nf3 nf11 nf10
i.mx51 applications processors for consumer and industrial products, rev. 6 52 freescale semiconductor electrical characteristics figure 17. read data latch timing?asymmetric mode figure 18. read data latch timing?symmetric mode nfce_b nfre_b nfrb_b nfio[15:0] data from nf nf13 nf15 nf14 nf17 nf12 nf16 nfce_b nfre_b nfrb_b nfio[15:0] data from nf nf13 nf15 nf14 nf12 nf16 nf18
electrical characteristics i.mx51 applications processors for consumer and industrial products, rev. 6 freescale semiconductor 53 figure 19. other timing parameters table 50. nfc?timing characteristics id parameter symbol asymmetric mode min symmetric mode min max nf1 nfcle setup time tcls 2t-1 2t-1 ? nf2 nfcle hold time tclh t-4.45 t-4.45 ? nf3 nfce_b setup time tcs 2t-1 t-1 ? nf4 nfce_b hold time tch 2t-5.55 0.5t-5.55 ? nf5 nfwe_b pulse width twp t-2.5 0.5t-1.5 ? nf6 nfale setup time tals 2t-2.7 2t-2.7 ? nf7 nfale hold time talh t-4.45 t-4.45 ? nf8 data setup time tds t-2.25 0.5t-2.25 ? nf9 data hold time tdh t-6.55 0.5t-5.55 ? nf10 write cycle time twc 2t t ? nf11 nfwe_b hold time twh t-1.25 0.5t-1.25 ? nf12 ready to nfre_b low trr 9t 9t ? nf13 nfre_b pulse width trp 1.5t-2.7 0.5t ? nf14 read cycle time trc 2t t ? nf15 nfre_b high hold time treh 0.5t-1.5 0.5t-1.5 ? nf16 1 data setup on read tdsr 11.2+0.5t-tdl 2 11.2-tdl 2 ? nf17 3 data hold on read tdhr 0 ? 2t aclk +t nf18 4 data hold on read tdhr ? tdl 2 2t aclk +t nf19 cle to re delay tclr 13t 13t ? nf20 ce to re delay tcre t-3.45 1.5t-3.45 ? nfcle nfce_b nfre_b nfrb_b nfwe_b nf20 nf19 nf21 nf22
i.mx51 applications processors for consumer and industrial products, rev. 6 54 freescale semiconductor electrical characteristics 4.6.7 external interface module (weim) the following sections provide information on the weim. 4.6.7.1 weim signal cross reference table 51 is a guide to help the user identify signals in the weim chapter of the i.mx51 multimedia applications processor reference manual (mcimx51rm) that are the same as those mentioned in this data sheet. nf21 we high to re low twhr 14t-5.45 14t-5.45 ? nf22 we high to busy twb ? ? 6t 1 t dsr is calculated by the following formula: asymmetric mode: t dsr = t repd + t dpd + 1 / 2 t ? tdl 2 symmetric mode: t dsr = t repd + t dpd ? tdl 2 t repd + t dpd = 11.2 ns (including clock skew) where t repd is re propogation delay in the chip including io pad delay, and t dpd is data propogation delay from io pad to emi including io pad delay. t dsr can be used to determine t rea max parameter with the following formula: t rea = 1.5t ? t dsr . 2 tdl is composed of 4 delay-line units each generates an equal delay with min 1.25 ns and max 1 aclk period (t aclk ). default is 1/4 aclk period for each delay-line unit, so all 4 delay lines together generates a total of 1 aclk period. t aclk is ?emi_slow_clk? of the system, which default value is 7.5 ns (133 mhz). 3 nf17 is defined only in asymmetric operation mode. nf17 max value is equivalent to max t rhz value that can be used with nfc. t aclk is ?emi_slow_clk? of the system. 4 nf18 is defined only in symmetric operation mode. t dhr (min) is calculated by the following formula: tdl 2 ? (t repd + t dpd ) where t repd is re propogation delay in the chip including io pad delay, and t dpd is data propogation delay from io pad to emi including io pad delay. nf18 max value is equivalent to max t rhz value that can be used with nfc. t aclk is ?emi_slow_clk? of the system. table 51. weim signal cross reference reference manual weim chapter nomenclature data sheet nomenclature, reference manual external signals and pin multiplexing chapter, and iomux controller chapter nomenclature bclk eim_bclk csx eim_csx we_b eim_rw oe_b eim_oe bey_b eim_ebx adv eim_lba table 50. nfc?timing characteristics (continued) id parameter symbol asymmetric mode min symmetric mode min max
electrical characteristics i.mx51 applications processors for consumer and industrial products, rev. 6 freescale semiconductor 55 4.6.7.2 weim internal module multiplexing table 52 provides weim internal muxing information. 38 4 addr eim_a[27:16], eim_da[15:0] addr/m_data eim_dax (addr/data muxed mode) data eim_nfc_d (data bus shared with nand flash) eim_dx (dedicated data bus) wait_b eim_wait table 52. weim interface pinout in various configurations non multiplexed address/data mode (mum=0) multiplexed address/data mode (mum=1) 8-bit (dsz=100) 8-bit (dsz=101) 8-bit 1 (dsz=110 ) 1 this mode is not supported due to erratum engcm11244. 8-bit (dsz=111 ) 16-bit (dsz=001) 16-bit (dsz=010) 32-bit (dsz=011 ) 16-bit (dsz=001) 32-bit (dsz=011) a[15:0] eim_da [15:0] eim_da [15:0] eim_da [15:0] eim_da [15:0] eim_da [15:0] eim_da [15:0] eim_da [15:0] eim_da [15:0] eim_da [15:0] a[27:16] eim_a [27:16] eim_a [27:16] eim_a [27:16] eim_a [27:16] eim_a [27:16] eim_a [27:16] eim_a [27:16] eim_a [27:16] nandf_d [11:0] d[7:0], eim_eb0 nandf_d [7:0] ? ? ? nandf_d [7:0] ? nandf_d [7:0] eim_da [7:0] eim_da [7:0] d[15:8], eim_eb1 ? nandf_d [15:8] ? ? nandf_d [15:8] ? nandf_d [15:8] eim_da [15:8] eim_da [15:8] d[23:16], eim_eb2 ??eim_d [23:16] ??eim_d [23:16] eim_d [23:16] ? nandf_d [7:0] d[31:24], eim_eb3 ???eim_d [31:24] ?eim_d [31:24] eim_d [31:24] ? nandf_d [15:8] table 51. weim signal cross reference (continued) reference manual weim chapter nomenclature data sheet nomenclature, reference manual external signals and pin multiplexing chapter, and iomux controller chapter nomenclature
i.mx51 applications processors for consumer and industrial products, rev. 6 56 freescale semiconductor electrical characteristics 4.6.7.3 general weim timing-synchronous mode figure 20 , figure 21 , and table 53 specify the timings related to the weim module. all weim output control signals may be asserted and deasserted by an internal clock synchronized to the bclk rising edge according to corresponding assertion/negation control fields. , figure 20. weim outputs timing diagram figure 21. weim inputs timing diagram table 53. weim bus timing parameters 1 id parameter bcd = 0 bcd = 1 bcd = 2 bcd = 3 min max min max min max min max we1 bclk cycle time 2 t 2 x t 3 x t 4 x t we2 bclk low level width 0.4 x t 0.8 x t 1.2 x t 1.6 x t we4 address csx_b we_b oe_b bclk bey_b adv_b output data ... we5 we6 we7 we8 we9 we10 we11 we12 we13 we14 we15 we16 we17 we3 we2 we1 input data wait_b bclk we19 we18 we21 we20
electrical characteristics i.mx51 applications processors for consumer and industrial products, rev. 6 freescale semiconductor 57 we3 bclk high level width 0.4 x t 0.8 x t 1.2 x t 1.6 x t we4 clock rise to address valid 3 -0.5 x t - 1.25 -0.5 x t + 1.75 -t - 1.25 -t + 1.75 -1.5 x t - 1.25 -1.5 x t +1.75 -2 x t - 1.25 -2 x t + 1.75 we5 clock rise to address invalid 0.5 x t - 1.25 0.5 x t + 1.75 t - 1.25 t + 1.75 1.5 x t - 1.25 1.5 x t + 1.75 2 x t - 1.25 2 x t + 1.75 we6 clock rise to csx_b valid -0.5 x t - 1.25 -0.5 x t + 1.75 -t - 1.25 -t + 1.75 -1.5 x t - 1.25 -1.5 x t + 1.75 -2 x t - 1.25 -2 x t + 1.75 we7 clock rise to csx_b invalid 0.5 x t - 1.25 0.5 x t + 1.75 t - 1.25 t + 1.75 1.5 x t - 1.25 1.5 x t + 1.75 2 x t - 1.25 2 x t + 1.75 we8 clock rise to we_b valid -0.5 x t - 1.25 -0.5 x t + 1.75 -t - 1.25 -t + 1.75 -1.5 x t - 1.25 -1.5 x t + 1.75 -2 x t - 1.25 -2 x t + 1.75 we9 clock rise to we_b invalid 0.5 x t - 1.25 0.5 x t + 1.75 t - 1.25 t + 1.75 1.5 x t - 1.25 1.5 x t + 1.75 2 x t - 1.25 2 x t + 1.75 we10 clock rise to oe_b valid -0.5 x t - 1.25 -0.5 x t + 1.75 -t - 1.25 -t + 1.75 -1.5 x t - 1.25 -1.5 x t + 1.75 -2 x t - 1.25 -2 x t + 1.75 we11 clock rise to oe_b invalid 0.5 x t - 1.25 0.5 x t + 1.75 t - 1.25 t + 1.75 1.5 x t - 1.25 1.5 x t + 1.75 2 x t - 1.25 2 x t + 1.75 we12 clock rise to bey_b valid -0.5 x t - 1.25 -0 .5 x t + 1.75 -t - 1.25 -t + 1.75 -1.5 x t - 1.25 -1.5 x t + 1.75 -2 x t - 1.25 -2 x t + 1.75 we13 clock rise to bey_b invalid 0.5 x t - 1.25 0.5 x t + 1.75 t - 1.25 t + 1.75 1.5 x t - 1.25 1.5 x t + 1.75 2 x t - 1.25 2 x t + 1.75 we14 clock rise to adv_b valid -0.5 x t - 1.25 -0.5 x t + 1.75 -t - 1.25 -t + 1.75 -1.5 x t - 1.25 -1.5 x t + 1.75 -2 x t - 1.25 -2 x t + 1.75 we15 clock rise to adv_b invalid 0.5 x t - 1.25 0.5 x t + 1.75 t - 1.25 t + 1.75 1.5 x t - 1.25 1.5 x t + 1.75 2 x t - 1.25 2 x t + 1.75 we16 clock rise to output data valid -0.5 x t - 1.25 -0.5 x t + 1.75 -t - 1.25 -t + 1.75 -1.5 x t - 1.25 -1.5 x t + 1.75 -2 x t - 1.25 -2 x t + 1.75 we17 clock rise to output data invalid 0.5 x t - 1.25 0.5 x t + 1.75 t - 1.25 t + 1.75 1.5 x t - 1.25 1.5 x t + 1.75 2 x t - 1.25 2 x t + 1.75 we18 input data setup time to clock rise 2 ns ? 4 ns ? ? ? ? ? we19 input data hold time from clock rise 2 ns ? 2 ns ? ? ? ? ? we20 wait_b setup time to clock rise 2 ns ? 4 ns ? ? ? ? ? we21 wait_b hold time from clock rise 2 ns ? 2 ns ? ? ? ? ? table 53. weim bus timing parameters (continued) 1 id parameter bcd = 0 bcd = 1 bcd = 2 bcd = 3 min max min max min max min max
i.mx51 applications processors for consumer and industrial products, rev. 6 58 freescale semiconductor electrical characteristics 4.6.7.4 examples of weim synchronous accesses figure 22 to figure 25 provide few examples of basic weim accesses to external memory devices with the timing parameters mentioned previously for specific control parameters settings. figure 22. synchronous memory read access, wsc=1 1 t is the maximal weim logic (axi_clk) cycle time. the maximum allowed axi_clk frequency is 133 mhz, whereas the maximum allowed bclk frequency is 104 mhz. as a result, if bcd = 0, axi_clk must be 104 mhz. if bcd = 1, then 133 mhz is allowed for axi_clk, resulting in a bclk of 66.5 mhz. when the clock branch to weim is decreased to 104 mhz, other busses are impacted which are clocked from this source. see the ccm chapter of the i.mx51 reference manual for a detailed clock tree description. 2 bclk parameters are being measured from the 50% point, that is, high is defined as 50% of signal value and low is defined as 50% as signal value. 3 for signal measurements ?high? is defined as 80% of signal value and ?low? is defined as 20% of signal value. last valid address address v1 d(v1) bclk addr data we_b adv_b oe_b bey_b csx_b we4 we5 we6 we7 we10 we11 we13 we12 we14 we15 we18 we19
electrical characteristics i.mx51 applications processors for consumer and industrial products, rev. 6 freescale semiconductor 59 figure 23. synchronous memory, write access, wsc=1, wbea=0, and wadvn=0 figure 24. muxed address/data (a/d) mode, synchronous write access, wsc=6, adva=0, advn=1, and adh=1 note in 32-bit muxed address/data (a/d) mode the 16 msbs are driven on the data bus. last valid address address v1 d(v1) bclk addr data we_b adv_b oe_b bey_b csx_b we4 we5 we6 we7 we8 we9 we12 we13 we14 we15 we16 we17 last bclk addr/ we_b adv_b oe_b bey_b csx_b address v1 write data valid addr m_data we4 we16 we6 we7 we9 we8 we10 we11 we14 we15 we17 we5
i.mx51 applications processors for consumer and industrial products, rev. 6 60 freescale semiconductor electrical characteristics figure 25. 16-bit muxed a/d mode, synchronous read access, wsc=7, radvn=1, adh=1, and oea=0 4.6.7.5 general weim timing-asynchronous mode figure 26 through figure 31 , and table 54 help to determine timing parameters relative to the chip select (cs) state for asynchronous and dtack weim accesses with corresponding weim bit fields and the timing parameters mentioned above. asynchronous read and write access length in cycles may vary from what is shown in figure 26 through figure 29 as rwsc, oen, and csn is configured differently. see i.mx51 reference manual for the weim programming model. last bclk addr/ we_b adv_b oe_b bey_b csx_b address v1 data valid addr m_data we5 we6 we7 we14 we15 we10 we11 we12 we13 we18 we19 we4
electrical characteristics i.mx51 applications processors for consumer and industrial products, rev. 6 freescale semiconductor 61 figure 26. asynchronous memory read access (rwsc = 5) figure 27. asynchronous a/d muxed read access (rwsc = 5) last valid address address v1 d(v1) addr/ data[7:0] we_b adv_b oe_b bey_b csx_b next address we39 we35 we37 we32 we36 we38 we43 we40 we31 we44 int_clk start of access end of access maxdi maxcso maxco m_data addr. v1 d(v1) addr/ we_b adv_b oe_b bey_b csx_b we39 we35a we37 we36 we38 we40a we31 we44 int_clk start of access end of access maxdi maxcso maxco we32a m_data
i.mx51 applications processors for consumer and industrial products, rev. 6 62 freescale semiconductor electrical characteristics figure 28. asynchronous memory write access figure 29. asynchronous a/d muxed write access last valid address address v1 d(v1) addr data we_b adv_b oe_b bey_b csx_b next address we31 we39 we33 we45 we32 we40 we34 we46 we42 we41 we_b oe_b bey_b csx_b we33 we45 we34 we46 we42 addr. v1 d(v1) addr/ we31 we42 we41a we32a m_data adv_b we39 we40a
electrical characteristics i.mx51 applications processors for consumer and industrial products, rev. 6 freescale semiconductor 63 figure 30. dtack read access (dap=0) figure 31. dtack write access (dap=0) last valid address address v1 d(v1) addr data[7:0] we_b adv_b oe_b bey_b csx_b next address we39 we35 we37 we32 we36 we38 we43 we40 we31 we44 dtack we47 we48 last valid address address v1 d(v1) addr data we_b adv_b oe_b bey_b csx_b next address we31 we39 we33 we45 we32 we40 we34 we46 we42 we41 dtack we47 we48
i.mx51 applications processors for consumer and industrial products, rev. 6 64 freescale semiconductor electrical characteristics table 54. weim asynchronous timing parameters table relative chip select ref no. parameter determination by synchronous measured parameters 12 min max (if 133 mhz is supported by soc) unit we31 csx_b valid to address valid we4 - we6 - csa 3 ? 3 - csa ns we32 address invalid to csx_b invalid we7 - we5 - csn 4 ?3 - c s nn s we32a( muxed a/d csx_b valid to address invalid t 5 + we4 - we7 + (advn + adva + 1 - csa 3 ) -3 + (advn + adva + 1 - csa) ?n s we33 csx_b valid to we_b valid we8 - we6 + (wea - csa) ? 3 + (wea - csa) ns we34 we_b invalid to csx_b invalid we7 - we9 + (wen - csn) ? 3 - (wen_csn) ns we35 csx_b valid to oe_b valid we10 - we6 + (oea - csa) ? 3 + (oea - csa) ns we35a (muxed a/d) csx_b valid to oe_b valid we10 - we6 + (oea + radvn + radva + adh + 1 - csa) -3 + (oea + radvn+radva+ adh+1-csa) 3 + (oea + radvn+radva+ad h+1-csa) ns we36 oe_b invalid to csx_b invalid we7 - we11 + (oen - csn) ? 3 - (oen - csn) ns we37 csx_b valid to bey_b valid (read access) we12 - we6 + (rbea - csa) ? 3 + (rbea 6 - csa) ns we38 bey_b invalid to csx_b invalid (read access) we7 - we13 + (rben - csn) ? 3 - (rben 7 - csn) ns we39 csx_b valid to adv_b valid we14 - we6 + (adva - csa) ? 3 + (adva - csa) ns we40 adv_b invalid to csx_b invalid (advl is asserted) we7 - we15 - csn ? 3 - csn ns we40a (muxed a/d) csx_b valid to adv_b invalid we14 - we6 + (advn + adva + 1 - csa) -3 + (advn + adva + 1 - csa) 3 + (advn + adva + 1 - csa) ns we41 csx_b valid to output data valid we16 - we6 - wcsa ? 3 - wcsa ns we41a (muxed a/d) csx_b valid to output data valid we16 - we6 + (wadvn + wadva + adh + 1 - wcsa) ? 3 + (wadvn + wadva + adh + 1 - wcsa) ns we42 output data invalid to csx_b invalid we17 - we7 - csn ? 3 - csn ns maxco output max. delay from internal driving addr/control ffs to chip outputs. 10 ? ? ns maxcs o output max. delay from csx internal driving ffs to csx out. 10 ? ? maxdi data maximum delay from chip input data to its internal ff 5??
electrical characteristics i.mx51 applications processors for consumer and industrial products, rev. 6 freescale semiconductor 65 we43 input data valid to csx_b invalid maxco - maxcso + maxdi maxco - maxcso + maxdi ?n s we44 csx_b invalid to input data invalid 00? n s we45 csx_b valid to bey_b valid (write access) we12 - we6 + (wbea - csa) ? 3 + (wbea - csa) ns we46 bey_b invalid to csx_b invalid (write access) we7 - we13 + (wben - csn) ? -3 + (wben - csn) ns maxdti dtack maximum delay from chip dtack input to its internal ff + 2 cycles for synchronization ??? we47 dtack active to csx_b invalid maxco - maxcso + maxdti maxco - maxcso + maxdti ?n s we48 csx_b invalid to dtack invalid 0 0 ? ns 1 parameters we4... we21 value see column bcd = 0 in table 53 . 2 all config. parameters (csa,csn,wbea,wben,adva,ad vn,oen,oea,rbea & rben) are in cycle units. 3 cs assertion. this bit field determines when cs signal is asserted during read/write cycles. 4 cs negation. this bit field determines when cs signal is negated during read/write cycles. 5 t is axi_clk cycle time. 6 be assertion. this bit field determines when be signal is asserted during read cycles. 7 be negation. this bit field determines when be signal is negated during read cycles. table 54. weim asynchronous timing parameters table relative chip select ref no. parameter determination by synchronous measured parameters 12 min max (if 133 mhz is supported by soc) unit
i.mx51 applications processors for consumer and industrial products, rev. 6 66 freescale semiconductor electrical characteristics 4.6.8 sdram controller timing parameters 4.6.8.1 mobile ddr sdram timing parameters figure 32 shows the basic timing parameters for mobile ddr (mddr) sdram. the timing parameters for this diagram is shown in table 55 . figure 32. mddr sdram basic timing parameters table 55. mddr sdram timing parameter table id parameter symbol 200 mhz 166 mhz 133 mhz unit min max min max min max dd1 sdram clock high-level width t ch 0.45 0.55 0.45 0.55 0.45 0.55 t ck dd2 sdram clock low-level width t cl 0.45 0.55 0.45 0.55 0.45 0.55 t ck dd3 sdram clock cycle time t ck 5?6?7.5?ns dd4 cs, ras, cas, cke, we setup time t is 1 1 this parameter is affected by pad timing. if the slew rate is < 1 v/ns, 0.2 ns should be added to the value. for cmos65 pads this is true for medium and low drive strengths. 0.9 ? 1.1 ? 1.3 ? ns dd5 cs, ras, cas, cke, we hold time t ih 1 0.9 ? 1.1 ? 1.3 ? ns dd6 address output setup time t is 1 0.9 ? 1.1 ? 1.3 ? ns dd7 address output hold time t ih 1 0.9 ? 1.1 ? 1.3 ? ns sdclk we addr row/ba col/ba cs cas ras dd1 dd3 dd2 dd4 dd4 dd4 dd5 dd5 dd5 dd5 dd6 dd7 sdclk
electrical characteristics i.mx51 applications processors for consumer and industrial products, rev. 6 freescale semiconductor 67 figure 33 shows the timing diagram for mddr sdram write cycle. the timing parameters for this diagram is shown in table 56 . figure 33. mddr sdram write cycle timing diagram table 56. mddr sdram write cycle parameter table 1 1 test conditions are: capacitance 15 pf for ddr pads. recommended drive strengths is medium for sdclk and high for address and controls. id parameter symbol 200 mhz 2 2 sdram clk and dqs related parameters are being measured from the 50% point. that is, high is defined as 50% of signal value and low is defined as 50% as signal value. ddr sdram clk parameters are measured at the crossing point of sdclk and sdclk (inverted clock). 166 mhz 133 mhz unit min max min max min max dd17 dq and dqm setup time to dqs t ds 3 3 this parameter is affected by pad timing. if the slew rate is < 1 v/ns, 0.1 ns should be increased to this value. 0.48 ? 0.6 ? 0.8 ? ns dd18 dq and dqm hold time to dqs t dh 1 0.48 ? 0.6 ? 0.8 ? ns dd19 write cycle dqs falling edge to sdclk output setup time t dss 0.2 ? 0.2 ? 0.2 ? tck dd20 write cycle dqs falling edge to sdclk output hold time t dsh 0.2 ? 0.2 ? 0.2 ? tck dd21 write command to first dqs latching transition t dqss 0.75 1.25 0.75 1.25 0.75 1.25 tck dd22 dqs high level width t dqsh 0.4 0.6 0.4 0.6 0.4 0.6 tck dd23 dqs low level width t dqsl 0.4 0.6 0.4 0.6 0.4 0.6 tck sdclk sdclk_b dqs (output) dq (output) dqm (output) data data data data data data data data dm dm dm dm dm dm dm dm dd17 dd17 dd17 dd17 dd18 dd18 dd18 dd18 dd19 dd20 dd21 dd23 dd22
i.mx51 applications processors for consumer and industrial products, rev. 6 68 freescale semiconductor electrical characteristics figure 34 shows the timing diagram for mddr sdram dq versus dqs and sdclk read cycle. the timing parameters for this diagram is shown in table 57 . figure 34. mddr sdram dq vs. dqs and sdclk read cycle timing diagram table 57. mddr sdram read cycle parameter table 1 1 test conditions are: capacitance 15 pf for ddr pads. recommended drive strengths is medium for sdclk and high for address and controls id parameter symbol 200 mhz 2 2 sdram clk and dqs related parameters are being measured from the 50% point. that is, high is defined as 50% of signal value and low is defined as 50% as signal value. ddr sdram clk parameters are measured at the crossing point of sdclk and sdclk (inverted clock) 166 mhz 133 mhz unit min max min max min max dd24 dqs - dq skew (defines the data valid window in read cycles related to dqs) t dqsq ? 0.4 ? 0.75 ? 0.85 ns dd25 dqs dq in hold time from dqs t qh 1.75 ? 2.05 ? 2.6 ? ns dd26 dqs output access time from sdclk posedge t dqsck 2 5 2 5.5 2 6.5 ns sdclk sdclk_b dqs (input) dq (input) data data data data data data data data dd26 dd24 dd25
electrical characteristics i.mx51 applications processors for consumer and industrial products, rev. 6 freescale semiconductor 69 4.6.9 ddr2 sdram specific parameters figure 35 shows the timing parameters for ddr2. the timing parameters for this diagram appear in table 58 . figure 35. ddr2 sdram basic timing parameters table 58. ddr2 sdram timing parameter table id parameter symbol sdclk = 200 mhz unit min max ddr1 sdram clock high-level width t ch 0.45 0.55 t ck ddr2 sdram clock low-level width t cl 0.45 0.55 t ck ddr3 sdram clock cycle time t ck 5?n s ddr4 cs, ras, cas, cke, we, odt setup time t is 1 1.5 ? ns ddr5 cs, ras, cas, cke, we, odt hold time t ih 1 1.7 ? ns sdclk we addr row/ba col/ba cs cas ras ddr1 ddr3 ddr2 ddr4 ddr4 ddr4 ddr5 ddr5 ddr5 ddr5 ddr6 ddr7 sdclk odt/cke ddr4
i.mx51 applications processors for consumer and industrial products, rev. 6 70 freescale semiconductor electrical characteristics note measurements are taken from vref to vref (cross-point to cross-point), but jedec timings for single-ended signals are defined from vref to vil(ac) max or to vih(ac) min. ddr6 address output setup time t is 1 1.7 ? ns ddr7 address output hold time t ih 1 1.5 ? ns 1 these values are for command/address slew rates of 1 v/ns and sdclk / sdclk_b differential slew rate of 2 v/ns. for different values use the settings shown in ta b l e 5 9 . table 59. derating values for ddr2-400 (sdclk = 200 mhz) command / address slew rate (v/ns) sdclk differential slew rates 1,2 unit 2.0 v/ns 1.5 v/ns 1.0 v/ns tls tlh tls tlh tls tlh 4.0 +187 +94 +217 +124 +247 +154 ps 3.5 +179 +89 +209 +119 +239 +149 ps 3.0 +167 +83 +197 +113 +227 +143 ps 2.5 +150 +75 +180 +105 +210 +135 ps 2.0 +125 +45 +155 +75 +185 +105 ps 1.5 +83 +21 +113 +51 +143 +81 ps 1.0 +0 +0 +30 +30 +60 +60 ps 0.9 ?11 ?14 +19 +16 +49 +46 ps 0.8 ?25 ?31 +5 ?1 +35 +29 ps 0.7 ?43 ?54 ?13 ?24 +17 +6 ps 0.6 ?67 ?83 ?37 ?53 ?7 ?23 ps 0.5 ?110 ?125 ?80 ?95 ?50 ?65 ps 0.4 ?175 ?188 ?145 ?158 ?115 ?128 ps 0.3 ?285 ?292 ?255 ?262 ?225 ?232 ps 0.25 ?350 ?375 ?320 ?345 ?290 ?315 ps 0.2 ?525 ?500 ?495 ?470 ?465 ?440 ps 0.15 ?800 ?708 ?770 ?678 ?740 ?648 ps 0.1 ?1450 ?1125 ?1420 ?1095 ?1390 ?1065 ps table 58. ddr2 sdram timing parameter table (continued) id parameter symbol sdclk = 200 mhz unit min max
electrical characteristics i.mx51 applications processors for consumer and industrial products, rev. 6 freescale semiconductor 71 figure 36 shows the timing diagram for ddr2 sdrm write cycle. the timing parameters for this diagram appear in table 60 . figure 36. ddr2 sdram write cycle timing diagram 1 test conditions are: capacitance 15 pf for ddr contacts. recommended drive strengths: medium for sdclk and high for address and controls. 2 sdclk and dqs related parameters are measured from the 50% point. for example, a high is defined as 50% of the signal value and a low is defined as 50% of the signal value. ddr sdram clk parameters are measured at the crossing point of sdclk and sdclk_b. table 60. ddr2 sdram write cycle parameter table id parameter symbol sdclk = 200 mhz unit min max ddr17 dq & dqm setup time to dqs t ds 0.8 1 1 - in order to meet these setup/hold values, write calibration should be performed to place the dqs in the middle of dq window. the minimum window width is 1.6ns (ddr17+ddr18). - from ddr controller perspective, the timing is the same for both differential and single ended mode. ?ns ddr18 dq & dqm hold time to dqs t dh 0.8 2 2 - in order to meet these setup/hold values, write calibration should be performed to place the dqs in the middle of dq window. the minimum window width is 1.6ns (ddr17+ddr18). - from ddr controller perspective, the timing is the same for both differential and single ended mode. ?ns ddr19 dqs falling edge to sdclk output setup time t dss 1.6 ? ns ddr20 dqs falling edge sdclk output hold time t dsh 2.4 ? ns ddr21 dqs latching rising transitions to associated clock edges t dqss -0.7 0.3 ns ddr22 dqs high level width t dqsh 0.35 ? tck ddr23 dqs low level width t dqsl 0.35 ? tck sdclk sdclk_b dqs (output) dq (output) dqm (output) data data data data data data data data dm dm dm dm dm dm dm dm ddr17 ddr17 ddr17 ddr17 ddr18 ddr18 ddr18 ddr18 ddr21 ddr23 ddr22 ddr20 ddr19
i.mx51 applications processors for consumer and industrial products, rev. 6 72 freescale semiconductor electrical characteristics note measurements are taken from vref to vref (cross-point to cross-point), but jedec timings for single-ended signals are defined from vref to vil(ac) max or to vih(ac) min. table 61. derating values for ddr2 differential dqs 1 , 2 table 62. derating values for ddr2 single ended dqs 3 , 4 1. test conditions are: capacitance 15 pf for ddr pads. recommended drive strengths is medium for sdclk and high for address and controls. 2. sdram clk and dqs related parameters are being measured from the 50% point. that is, high is defined as 50% of signal value and low is defined as 50% as signal value. ddr sdram clk parameters are measured at the crossing point of sdclk and sdclk (inverted clock). 3. test conditions are: capacitance 15 pf for ddr pads. recommended drive strengths is medium for sdclk and high for address and controls. 4. sdram clk and dqs related parameters are being measured from the 50% point. that is, high is defined as 50% of signal value and low is defined as 50% as signal value. ddr sdram clk parameters are measured at the crossing point of sdclk and sdclk (inverted clock).
electrical characteristics i.mx51 applications processors for consumer and industrial products, rev. 6 freescale semiconductor 73 figure 37 shows the timing diagram for ddr2 sdrm read cycle. the timing parameters for this diagram appear in table 63 . figure 37. ddr2 sdram dq versus dqs and sdclk read cycle timing diagram note it is recommended to perform read calibration process in order to achieve the best performance. table 63. ddr2 sdram read cycle parameter table id parameter symbol sdclk = 200 mhz unit min max ddr24 1 1 the actual timing may vary depending on read calibration settings. what is actually important for the controller is ddr25-ddr24 which results in the minimum required dq valid window width: 1.8ns-0.5ns = 1.3ns of minimum width. dqs?dq skew (defines the data valid window during read cycles related to dqs). t dqsq ?0.5ns ddr25 2 2 the actual timing may vary depending on read calibration settings. what is actually important for the controller is ddr25-ddr24 which results in the minimum required dq valid window width: 1.8ns-0.5ns = 1.3ns of minimum width. dq hold time from dqs t qh 1.8 ? ns sdclk sdclk_b dqs (input) dq (input) data data data data data data data data ddr25 ddr24
i.mx51 applications processors for consumer and industrial products, rev. 6 74 freescale semiconductor electrical characteristics 4.7 external peripheral interfaces the following sections provide information on external peripheral interfaces. 4.7.1 cspi timing parameters this section describes the timing parameters of the cspi. the cspi has separate timing parameters for master and slave modes. the nomenclature used with the cspi modules and the respective routing of these signals is shown in table 64 . 4.7.1.1 cspi master mode timing figure 38 depicts the timing of cspi in master mode and table 65 lists the cspi master mode timing characteristics. figure 38. cspi master mode timing diagram table 64. cspi nomenclature and routing module i/o access ecspi1 cspi1 1 , usbh1, and di1 via iomux 1 this set of bga contacts is labeled cspi, but is actually an ecspi channel ecspi2 nandf and usbh1 via iomux cspi nandf, usbh1, sd1, sd2, and gpio via iomux table 65. cspi master mode timing parameters id parameter symbol min max unit cs1 sclk cycle time t clk 60 ? ns cs2 sclk high or low time t sw 26 ? ns cs3 sclk rise or fall 1 t rise/fall ??n s cs4 ssx pulse width t cslh 26 ? ns cs1 cs7 cs2 cs2 cs4 cs6 cs5 cs8 cs9 sclk ssx mosi miso rdy cs10 cs3 cs3
electrical characteristics i.mx51 applications processors for consumer and industrial products, rev. 6 freescale semiconductor 75 4.7.1.2 cspi slave mode timing figure 39 depicts the timing of cspi in slave mode. table 66 lists the cspi slave mode timing characteristics. figure 39. cspi slave mode timing diagram cs5 ssx lead time (slave select setup time) t scs 26 ? ns cs6 ssx lag time (ss hold time) t hcs 26 ? ns cs7 mosi propagation delay (c load =20pf) t pdmosi ?1 21 ns cs8 miso setup time t smiso 5?n s cs9 miso hold time t hmiso 5?n s cs10 rdy to ssx time 2 t sdry 5?n s 1 see specific i/o ac parameters section 4.5, ?i/o ac parameters ? 2 spi_rdy is sampled internally by ipg_clk and is asynchronous to all other cspi signals. table 66. cspi slave mode timing parameters id parameter symbol min max unit cs1 sclk cycle time t clk 60 ? ns cs2 sclk high or low time t sw 26 ? ns cs4 ssx pulse width t cslh 26 ? ns cs5 ssx lead time (ss setup time) t scs 26 ? ns cs6 ssx lag time (ss hold time) t hcs 26 ? ns cs7 mosi setup time t smosi 5?n s table 65. cspi master mode timing parameters (continued) id parameter symbol min max unit cs1 cs7 cs8 cs2 cs2 cs4 cs6 cs5 cs9 sclk ssx miso mosi
i.mx51 applications processors for consumer and industrial products, rev. 6 76 freescale semiconductor electrical characteristics 4.7.2 ecspi timing parameters this section describes the timing parameters of the ecspi. the ecspi has separate timing parameters for master and slave modes. the nomenclature used with the cspi modules and the respective routing of these signals is shown in table 64 . 4.7.2.1 ecspi master mode timing figure 40 depicts the timing of ecspi in master mode and table 67 lists the ecspi master mode timing characteristics. figure 40. ecspi master mode timing diagram cs8 mosi hold time t hmosi 5?n s cs9 miso propagation delay (c load =20pf) t pdmiso 03 5n s table 67. ecspi master mode timing parameters id parameter symbol min max unit cs1 ecspix_clk cycle time?read ecspix_clk cycle time?write t clk 60 15 ?ns cs2 ecspix_clk high or low time t sw 6?n s cs3 ecspix_clk rise or fall t rise/fall ??n s cs4 ecspix_cs_x pulse width t cslh 15 ? ns cs5 ecspix_cs_x lead time (cs setup time) t scs 5?n s cs6 ecspix_cs_x lag time (cs hold time) t hcs 5?n s cs7 ecspix_do setup time t smosi 5?n s table 66. cspi slave mode timing parameters (continued) id parameter symbol min max unit cs1 cs7 cs8 cs2 cs2 cs4 cs6 cs5 cs9 cs10 ecspix_clk ecspix_cs_x ecspix_do ecspix_di ecspix_dryn1 cs11 cs3 cs3
electrical characteristics i.mx51 applications processors for consumer and industrial products, rev. 6 freescale semiconductor 77 4.7.2.2 ecspi slave mode timing figure 41 depicts the timing of ecspi in slave mode and table 68 lists the ecspi slave mode timing characteristics. figure 41. ecspi slave mode timing diagram cs8 ecspix_do hold time t hmosi 5?n s cs9 ecspix_di setup time t smiso 5?n s cs10 ecspix_di hold time t hmiso 5?n s cs11 ecspix_dryn setup time t sdry 5?n s table 68. ecspi slave mode timing parameters id parameter symbol min max unit cs1 ecspix_clk cycle time?read ecspix_clk cycle time?write t clk 60 15 ?ns cs2 ecspix_clk high or low time t sw 6?n s cs3 ecspix_clk rise or fall t rise/fall ??n s cs4 ecspix_cs_x pulse width t cslh 15 ? ns cs5 ecspix_cs_x lead time (cs setup time) t scs 5?n s cs6 ecspix_cs_x lag time (cs hold time) t hcs 5?n s cs7 ecspix_do setup time t smosi 5?n s cs8 ecspix_do hold time t hmosi 5?n s cs9 ecspix_di setup time t smiso 5?n s cs10 ecspix_di hold time t hmiso 5?n s table 67. ecspi master mode timing parameters (continued) id parameter symbol min max unit cs1 cs7 cs8 cs2 cs2 cs4 cs6 cs5 cs9 cs10 ecspix_clk ecspix_cs_x ecspix_di ecspix_do cs3 cs3
i.mx51 applications processors for consumer and industrial products, rev. 6 78 freescale semiconductor electrical characteristics 4.7.3 esdhcv2 timing parameters this section describes the electrical information of the esdhcv2. figure 42 depicts the timing of esdhcv2, and table 69 lists the esdhcv2 timing characteristics. figure 42. esdhcv2 timing table 69. esdhcv2 interface timing specification id parameter symbols min max unit card input clock sd1 clock frequency (low speed) f pp 1 0400khz clock frequency (sd/sdio full speed/high speed) f pp 2 0 25/50 mhz clock frequency (mmc full speed/high speed) f pp 3 0 20/52 mhz clock frequency (identification mode) f od 100 400 khz sd2 clock low time t wl 7?ns sd3 clock high time t wh 7?ns sd4 clock rise time t tlh ?3ns sd5 clock fall time t thl ?3ns esdhc output/card inputs cmd, dat (reference to clk) sd6 4 esdhc output delay t od ?33ns esdhc input / card outputs cmd, dat (reference to clk) sd1 sd3 sd5 sd4 sd7 mmcx_cmd output from esdhcv2 to card mmcx_dat_1 ...... mmcx_dat_7 mmcx_dat_0 mmcx_cmd input from card to esdhcv2 mmcx_dat_1 ...... mmcx_dat_3 mmcx_dat_0 mmcx_clk sd2 sd8 sd6
electrical characteristics i.mx51 applications processors for consumer and industrial products, rev. 6 freescale semiconductor 79 4.7.4 fec ac timing parameters this section describes the electrical information of the fast ethernet controller (fec) module. the fec is designed to support both 10 and 100 mbps etherne t/ieee 802.3 networks. an external transceiver interface and transceiver function are required to comp lete the interface to the media. the fec supports the 10/100 mbps mii (18 pins in total) and the 10 mbps-only 7-wire interface, which uses 7 of the mii pins, for connection to an external ethernet transc eiver. for the pin list of mii and 7-wire, see i.mx51 multimedia applications processor reference manual (mcimx51rm). this section describes the ac timing specifications of the fec. 4.7.4.1 mii receive signal timing the mii receive signal timing involves the fec_rxd[3:0], fec_rx_dv, fec_rx_er, and fec_rx_clk signals. the receiver functions correctly up to a fec_rx_clk maximum frequency of 25 mhz + 1%. there is no minimum frequency requirement but the processor clock frequency must exceed twice the fec_rx_clk frequency. table 70 lists the mii receive channel signal timing parameters and figure 43 shows mii receive signal timings. . sd7 esdhc input setup time t isu 2.5 ? ns sd8 esdhc input hold time t ih 5 2.5 ? ns 1 in low speed mode, card clock must be lower than 400 khz, voltage ranges from 2.7 to 3.6 v. 2 in normal speed mode for sd/sdio card, clock frequency can be any value between 0 ? 25 mhz. in high-speed mode, clock frequency can be any value between 0 ? 50 mhz. 3 in normal speed mode for mmc card, clock frequency can be any value between 0 ? 20 mhz. in high-speed mode, clock frequency can be any value between 0 ? 52 mhz. 4 measurement taken with cload = 20 pf 5 to satisfy hold timing, the delay difference between clock input and cmd/data input must not exceed 2 ns. table 70. mii receive signal timing num characteristic 1 1 fec_rx_dv, fec_rx_clk, and fec_rxd0 have same timing in 10 mbps 7-wire interface mode. min max unit m1 fec_rxd[3:0], fec_rx_dv, fec_rx_er to fec_rx_clk setup 5 ? ns m2 fec_rx_clk to fec_rxd[3:0], fec_rx_dv, fec_rx_er hold 5 ? ns m3 fec_rx_clk pulse width high 35% 65% fec_rx_clk period m4 fec_rx_clk pulse width low 35% 65% fec_rx_clk period table 69. esdhcv2 interface ti ming specification (continued) id parameter symbols min max unit
i.mx51 applications processors for consumer and industrial products, rev. 6 80 freescale semiconductor electrical characteristics figure 43. mii receive signal timing diagram 4.7.4.2 mii transmit signal timing the mii transmit signal timing affects the fec_txd[3:0], fec_tx_en, fec_tx_er, and fec_tx_clk signals. the transmitter functions correctly up to a fec_tx_clk maximum frequency of 25 mhz + 1%. there is no minimum frequency requirement. in addition, the processor clock frequency must exceed twice the fec_tx_clk frequency. table 71 lists mii transmit channel timing parameters and figure 44 shows mii transmit signal timing diagram for the values listed in table 71 . . figure 44. mii transmit signal timing diagram table 71. mii transmit signal timing num characteristic 1 1 fec_tx_en, fec_tx_clk, and fec_txd0 have the same timing in 10 mbps 7-wire interface mode. min max unit m5 fec_tx_clk to fec_txd[3:0], fec_tx_en, fec_tx_er invalid 5 ? ns m6 fec_tx_clk to fec_txd[3:0], fec_tx_en, fec_tx_er valid ? 20 ns m7 fec_tx_clk pulse width high 35% 65% fec_tx_clk period m8 fec_tx_clk pulse width low 35% 65% fec_tx_clk period fec_rx_clk (input) fec_rxd[3:0] (inputs) fec_rx_dv fec_rx_er m3 m4 m1 m2 fec_tx_clk (input) fec_txd[3:0] (outputs) fec_tx_en fec_tx_er m7 m8 m5 m6
electrical characteristics i.mx51 applications processors for consumer and industrial products, rev. 6 freescale semiconductor 81 4.7.4.3 mii async inputs signal timing (fec_crs and fec_col) table 72 lists mii asynchronous inputs signal timing information. figure 45 shows mii asynchronous input timings listed in table 72 . . figure 45. mii async inputs timing diagram 4.7.4.4 mii serial management channel timing (fec_mdio and fec_mdc) table 73 lists mii serial management channel timings. figure 46 shows mii serial management channel timings listed in table 73 . the mdc frequency should be equal to or less than 2.5 mhz to be compliant with the ieee 802.3 mii specification. however the fec can function correctly with a maximum mdc frequency of 15 mhz. table 72. mii async inputs signal timing num characteristic min max unit m9 1 1 fec_col has the same timing in 10 mbit 7-wire interface mode. fec_crs to fec_col minimum pulse width 1.5 ? fec_tx_clk period table 73. mii transmit signal timing id characteristic min max unit m10 fec_mdc falling edge to fec_mdio output invalid (minimum propagation delay) 0 ? ns m11 fec_mdc falling edge to fec_mdio output valid (max propagation delay) ? 5 ns m12 fec_mdio (input) to fec_mdc rising edge setup 18 ? ns m13 fec_mdio (input) to fec_mdc rising edge hold 0 ? ns m14 fec_mdc pulse width high 40% 60% fec_mdc period m15 fec_mdc pulse width low 40% 60% fec_mdc period fec_crs, fec_col m9
i.mx51 applications processors for consumer and industrial products, rev. 6 82 freescale semiconductor electrical characteristics figure 46. mii serial management channel timing diagram 4.7.5 frequency pre-multiplier (fpm) electrical parameters (ckil) the fpm is a dpll that converts a signal operating in the kilohertz region into a clock signal operating in the megahertz region. the output of the fpm provides the reference frequency for the on-chip dplls. parameters of the fpm are listed in table 74 . 4.7.6 high-speed i 2 c (hs-i 2 c) timing parameters this section describes the timing parameters of the hs-i 2 c module. this module can operate in the following modes: standard, fast and high speed. note see the errata for the hs-i 2 c module in the i.mx51 chip errata. there are two standard i 2 c modules that have no errata. table 74. fpm specifications parameter min typ max unit reference clock frequency range?ckil 32 32.768 256 khz fpm output clock frequency range 8 ? 33 mhz fpm multiplication factor (test condition is changed by a factor of 2) 128 ? 1024 ? lock-in time 1 1 plrf = 1 cycle assumed missed + x cycles for reset deassert + y cycles for calibration and lock x[ts] = {2,3,5,9}; y[ts] = {7,8,10,14}; where ts is the chosen time scale of the reference clock. in this case reference clock = 32 khz which makes ts = 0, therefore total time required for achieving lock is 10(1+2+7) cycles or 312.5 s. ? ? 312.5 s cycle-to-cycle frequency jitter (peak to peak) ? 8 20 ns fec_mdc (output) fec_mdio (output) m14 m15 m10 m11 m12 m13 fec_mdio (input)
electrical characteristics i.mx51 applications processors for consumer and industrial products, rev. 6 freescale semiconductor 83 4.7.6.1 standard and fast mode timing parameters figure 47 depicts the standard and fast mode timings of hs-i 2 c module, and table 75 lists the timing characteristics. figure 47. hs-i 2 c standard and fast mode bus timing table 75 . hs-i 2 c timing parameters?standard and fast mode id parameter standard mode fast mode unit min max min max ic1 sclh cycle time 10 ? 2.5 ? s ic2 hold time (repeated) start condition 4.0 ? 0.6 ? s ic3 set-up time for stop condition 4.0 ? 0.6 ? s ic4 data hold time 0 1 1 a device must internally provide a hold time of at least 300 ns for sdah signal in order to bridge the undefined region of the falling edge of sclh. 3.45 2 2 the maximum hold time has only to be met if the device does not stretch the low period (id no ic6) of the sclh signal 0 1 0.9 2 s ic5 high period of sclh clock 4.0 ? 0.6 ? s ic6 low period of the sclh clock 4.7 ? 1.3 ? s ic7 set-up time for a repeated start condition 4.7 ? 0.6 ? s ic8 data set-up time 250 ? 100 3 3 a fast-mode i 2 c-bus device can be used in a standard-mode i 2 c-bus system, but the requirement of set-up time (id no ic8) of 250 ns must then be met. this automatically is the case if the device does not stretch the low period of the sclh signal. if such a device does stretch the low period of the sclh signal, it must output the next data bit to the sdah line max_rise_tim e (id no ic10) + data_setup_time (id no ic8) = 1000 + 250 = 1250 ns (according to the standard-mode i 2 c-bus specification) before the sclh line is released. ?ns ic9 bus free time between a stop and start condition 4.7 ? 1.3 ? s ic10 rise time of both sdah and sclh signals ? 1000 20+0.1c b 4 4 c b = total capacitance of one bus line in pf. 300 ns ic11 fall time of both sdah and sclh signals ? 300 20+0.1c b 4 300 ns ic12 capacitive load for each bus line (c b ) ? 100 ? 100 pf ic10 ic11 ic9 ic2 ic8 ic4 ic7 ic3 ic6 ic10 ic5 ic11 start stop start start sdah sclh ic1
i.mx51 applications processors for consumer and industrial products, rev. 6 84 freescale semiconductor electrical characteristics 4.7.6.2 high-speed mode timing parameters figure 48 depicts the high-speed mode timings of hs-i 2 c module, and table 76 lists the timing characteristics. figure 48. high-speed mode timing table 7 6. hs-i 2 c high-speed mode timing parameters id parameter high-speed mode unit min max ic1 sclh cycle time 10 3.4 mhz ic2 setup time (repeated) start condition 160 ? ns ic3 hold time (repeated) start condition 160 ? ns ic4 low period of the sclh clock 160 ? ns ic5 high period of sclh clock 60 ? ns ic6 data set-up time 10 ? ns ic7 data hold time 0 1 1 a device must internally provide a hold time of at least 300 ns for sdah signal in order to bridge the undefined region of the falling edge of sclh. 70 ns ic8 rise time of sclh 10 40 ns ic9 rise time of sclh signal after a repeated start condition and after an acknowledge bit 10 80 ns ic10 fall time of sclh signal 10 40 ns ic11 rise time of sdah signal 10 80 ns ic12 fall time of sdah signal 10 80 ns ic13 set-up time for stop condition 160 ? ns ic14 capacitive load for each bus line (c b ) ? 100 pf ic11 ic12 ic3 ic6 ic7 ic2 ic13 ic4 ic9 ic5 ic10 start stop start start sdah sclh ic1 ic8
electrical characteristics i.mx51 applications processors for consumer and industrial products, rev. 6 freescale semiconductor 85 4.7.7 i 2 c module timing parameters this section describes the timing parameters of the i 2 c module. figure 49 depicts the timing of i 2 c module, and table 77 lists the i 2 c module timing characteristics. figure 49. i 2 c bus timing table 77 . i 2 c module timing parameters id parameter standard mode supply voltage = 1.65 v?1.95 v, 2.7 v?3.3 v fast mode supply voltage = 2.7 v?3.3 v unit min max min max ic1 i2clk cycle time 10 ? 2.5 ? s ic2 hold time (repeated) start condition 4.0 ? 0.6 ? s ic3 set-up time for stop condition 4.0 ? 0.6 ? s ic4 data hold time 0 1 1 a device must internally provide a hold time of at least 300 ns for i2dat signal in order to bridge the undefined region of the falling edge of i2clk. 3.45 2 2 the maximum hold time has only to be met if the device does not stretch the low period (id no ic5) of the i2clk signal 0 1 0.9 2 s ic5 high period of i2clk clock 4.0 ? 0.6 ? s ic6 low period of the i2clk clock 4.7 ? 1.3 ? s ic7 set-up time for a repeated start condition 4.7 ? 0.6 ? s ic8 data set-up time 250 ? 100 3 3 a fast-mode i2c-bus device can be used in a standard-mode i2c-bus system, but the requirement of set-up time (id no ic7) of 250 ns must be met. this automatically is the case if the device does not stretch the low period of the i2clk signal. if such a device does stretch the low period of the i2clk signal, it must output the next data bit to the i2dat line max_rise_time (ic9) + data_setup_time (ic7) = 1000 + 250 = 1250 ns (according to the standard-mode i2c-bus specification) before the i2clk line is released. ?ns ic9 bus free time between a stop and start condition 4.7 ? 1.3 ? s ic10 rise time of both i2dat and i2clk signals ? 1000 20 + 0.1c b 4 4 c b = total capacitance of one bus line in pf. 300 ns ic11 fall time of both i2dat and i2clk signals ? 300 20 + 0.1c b 4 300 ns ic12 capacitive load for each bus line (c b ) ? 400 ? 400 pf ic10 ic11 ic9 ic2 ic8 ic4 ic7 ic3 ic6 ic10 ic5 ic11 start stop start start i2dat i2clk ic1
i.mx51 applications processors for consumer and industrial products, rev. 6 86 freescale semiconductor electrical characteristics 4.7.8 image processing unit (ipu) module parameters the purpose of the ipu is to provide comprehensive support for the flow of data from an image sensor and/or to a display device. this support covers all aspects of these activities: ? connectivity to relevant devices ? cameras, displays, graphics acc elerators, and tv encoders. ? related image processing and manipulation: di splay processing, image conversions, and other related functions. ? synchronization and control capabilities such as avoidance of tearing artifacts. 4.7.8.1 sensor interface timings there are three camera timing modes supported by the ipu. 4.7.8.1.1 bt.656 and bt.1120 video mode smart camera sensors, which include imaging processing, usually support video mode transfer. they use an embedded timing syntax to replace the sensb_vsync and sensb_hsync signals. the timing syntax is defined by the bt.656/bt.1120 standards. this operation mode follows the recommendations of itu bt.656/ itu bt.1120 specifications. the only control signal used is sensb_pix_clk. start-of-frame and active-line signals are embedded in the data stream. an active line starts with a sav code and ends with a eav code. in some cases, digital blanking is inserted in between eav and sav code. the csi decodes and filters out the timing-coding from the data stream, thus recovering sensb_vsync and sensb_hs ync signals for internal use. on bt.656 one component per cycle is received over the sensb_data bus. on bt.1120 two components per cycle are received over the sensb_data bus. 4.7.8.1.2 gated clock mode the sensb_vsync, sensb_hsync, and sensb_pix_clk signals are used in this mode. see figure 50 . figure 50. gated clock mode timing diagram sensb_vsync sensb_hsync sensb_pix_clk sensb_data[19:0] invalid 1st byte n+1th frame invalid 1st byte nth frame active line start of frame
electrical characteristics i.mx51 applications processors for consumer and industrial products, rev. 6 freescale semiconductor 87 a frame starts with a rising edge on sensb_vsync (a ll the timings correspond to straight polarity of the corresponding signals). then sensb_hsync goes to high and hold for the entire line. pixel clock is valid as long as sensb_hsync is high. data is latche d at the rising edge of the valid pixel clocks. sensb_hsync goes to low at the end of line. pixe l clocks then become invalid and the csi stops receiving data from the stream. for next line the sensb_hsync timing repeats. for next frame the sensb_vsync timing repeats. 4.7.8.1.3 non-gated clock mode the timing is the same as the gated-clock mode (described in section 4.7.8.1.2, ?gated clock mode? ), except for the sensb_hsync signal, which is not used. see figure 51 . all incoming pixel clocks are valid and cause data to be latche d into the input fifo. the sensb_pix_clk signal is inactive (states low) until valid data is going to be transmitted over the bus. figure 51. non-gated clock mode timing diagram the timing described in figure 51 is that of a typical sensor. some other sensors may have a slightly different timing. the csi can be programmed to support rising/falling-edge triggered sensb_vsync; active-high/low sensb_hsync; and rising/fa lling-edge triggered sensb_pix_clk. 4.7.8.2 electrical characteristics figure 52 shows the sensor interface timing diagram. sensb_pix_clk signal described here is not generated by the ipu. table 78 shows the timing characteristics for the diagram shown in figure 52 . figure 52. sensor interface timing diagram sensb_vsync sensb_pix_clk sensb_data[19:0] invalid 1st byte n+1th frame invalid 1st byte nth frame start of frame ip3 sensb_data, sensb_vsync, ip2 1/ip1 sensb_pix_clk (sensor output) sensb_hsync
i.mx51 applications processors for consumer and industrial products, rev. 6 88 freescale semiconductor electrical characteristics 4.7.8.3 ipu display interface signal mapping the ipu supports a number of display output video formats. table 79 defines the mapping of the display interface pins used during various supported video interface formats. table 78. sensor interface timing characteristics id parameter symbol min max unit ip1 sensor output (pixel) clock frequency fpck 0.01 120 mhz ip2 data and control setup time tsu 3 ? ns ip3 data and control holdup time thd 2 ? ns
electrical characteristics i.mx51 applications processors for consumer and industrial products, rev. 6 freescale semiconductor 89 table 79. video signal cross-reference i.mx51 lcd comment 1 port name (x=1,2) rgb, signal name (general) rgb/tv signal allocation (example) smart 16-bit rgb 18-bit rgb 24-bit rgb 8-bit ycrcb 2 16-bit ycrcb 20-bit ycrcb signal name dispx_dat0 dat[0] b[0] b[0] b[0] y/c[0] c[0] c[0] dat[0] the restrictions are as follows: a) there are maximal three continuous groups of bits that could be independently mapped to the external bus. groups should not be overlapped. b) the bit order is expressed in each of the bit groups, for example b[0] = least significant blue pixel bit dispx_dat1 dat[1] b[1] b[1] b[1] y/c[1] c[1] c[1] dat[1] dispx_dat2 dat[2] b[2] b[2] b[2] y/c[2] c[2] c[2] dat[2] dispx_dat3 dat[3] b[3] b[3] b[3] y/c[3] c[3] c[3] dat[3] dispx_dat4 dat[4] b[4] b[4] b[4] y/c[4] c[4] c[4] dat[4] dispx_dat5 dat[5] g[0] b[5] b[5] y/c[5] c[5] c[5] dat[5] dispx_dat6 dat[6] g[1] g[0] b[6] y/c[6] c[6] c[6] dat[6] dispx_dat7 dat[7] g[2] g[1] b[7] y/c[7] c[7] c[7] dat[7] dispx_dat8 dat[8] g[3] g[2] g[0] ? y[0] c[8] dat[8] dispx_dat9 dat[9] g[4] g[3] g[1] ? y[1] c[9] dat[9] dispx_dat10 dat[10] g[5] g[4] g[2] ? y[2] y[0] dat[10] dispx_dat11 dat[11] r[0] g[5] g[3] ? y[3] y[1] dat[11] dispx_dat12 dat[12] r[1] r[0] g[4] ? y[4] y[2] dat[12] dispx_dat13 dat[13] r[2] r[1] g[5] ? y[5] y[3] dat[13] dispx_dat14 dat[14] r[3] r[2] g[6] ? y[6] y[4] dat[14] dispx_dat15 dat[15] r[4] r[3] g[7] ? y[7] y[5] dat[15] dispx_dat16 dat[16] ? r[4] r[0] ? ? y[6] ? dispx_dat17 dat[17] ? r[5] r[1] ? ? y[7] ? dispx_dat18 dat[18] ? ? r[2] ? ? y[8] ? dispx_dat19 dat[19] ? ? r[3] ? ? y[9] ? dispx_dat20 dat[20] ? ? r[4] ? ? ? ? dispx_dat21 dat[21] ? ? r[5] ? ? ? ?
i.mx51 applications processors for consumer and industrial products, rev. 6 90 freescale semiconductor electrical characteristics dispx_dat22 dat[22] ? ? r[6] ? ? ? ? ? dispx_dat23 dat[23] ? ? r[7] ? ? ? ? ? dix_disp_clk pixclk ? ? dix_pin1 ? vsync_in may be required for anti-tearing dix_pin2 hsync ? ? dix_pin3 vsync ? vsync out dix_pin4 ? ? additional frame/row synchronous signals with programmable timing dix_pin5 ? ? dix_pin6 ? ? dix_pin7 ? ? dix_pin8 ? ? dix_d0_cs ? cs0 ? dix_d1_cs ? cs1 alternate mode of pwm output for contrast or brightness control dix_pin11 ? wr ? dix_pin12 ? rd ? dix_pin13 ? rs1 register select signal dix_pin14 ? rs2 optional rs2 dix_pin15 drdy/dv drdy data validation/blank, data enable dix_pin16 ? ? additional data synchronous signals with programmable features/timing dix_pin17 q ? 1 signal mapping (both data and control/synchronization) is flexible. the table provides examples. 2 this mode works in compliance with recommendation itu-r bt.656. the timing reference signals (frame start, frame end, line start, and line end) are embedded in the 8-bit data bus. only video data is supported, transmission of non-video related data during blanking intervals is not supported. table 79. video signal cross-reference (continued) i.mx51 lcd comment 1 port name (x=1,2) rgb, signal name (general) rgb/tv signal allocation (example) smart 16-bit rgb 18-bit rgb 24-bit rgb 8-bit ycrcb 2 16-bit ycrcb 20-bit ycrcb signal name
electrical characteristics i.mx51 applications processors for consumer and industrial products, rev. 6 freescale semiconductor 91 4.7.8.4 ipu display interface timing the ipu display interface supports two kinds of display?s accesses: synchronous and asynchronous. there are two groups of external interface pins to provide synchronous and asynchronous controls accordantly. 4.7.8.4.1 synchronous controls the synchronous control is a signal that changes its value as a function either of a system or of an external clock. this control has a permanent period and a permanent wave form. there are special physical outputs to provide synchronous controls: ? the ipp_disp_clk is a dedicated base synchronous si gnal that is used to generate a base display (component, pixel) clock for a display. ? the ipp_pin_1? ipp_pin_7 are general purpose synchronous pins, that can be used to provide hsync, vsync, drdy or any else independent signal to a display. the ipu has a system of internal binding counters fo r internal events (like hsync/vsycn and so on) calculation. the internal event (local start point) is synchronized with internal di_clk. a suitable control starts from the local start point with predefined up and down values to calculate control?s changing points with half di_clk resolution. a full description of the counters system is in the ipu chapter of the i.mx51 multimedia applications processor reference manual (mcimx51rm) . 4.7.8.4.2 asynchronous controls the asynchronous control is a data oriented signal that changes its a value with an output data according to an additional internal flags coming with the data. there are special physical outputs to pr ovide asynchronous controls, as follows: ? the ipp_d0_cs and ipp_d1_cspins are dedicated to pr ovide chip select signals to two displays ? the ipp_pin_11? ipp_pin_17 are general purpose asynchronous pins, that can be used to provide wr. rd, rs or any else data oriented signal to display. note the ipu has independent signal ge nerators for asynchronous signals toggling. when a di decides to put a new asynchronous data in the bus, a new internal start (local start point) is generated. the signals generators calculate predefined up and down values to change pins states with half di_clk resolution. 4.7.8.5 synchronous interfaces to standard active matrix tft lcd panels 4.7.8.5.1 ipu display operating signals the ipu uses four control signals and data to operate a standard synchronous interface: ? ipp_disp_clk?clock to display ? hsync?horizontal synchronization
i.mx51 applications processors for consumer and industrial products, rev. 6 92 freescale semiconductor electrical characteristics ? vsync?vertical synchronization ? drdy?active data all synchronous display controls are generated on base of an internal generated ?local start point?. the synchronous display controls can be placed on time axis with di?s offset, up and down parameters. the display access can be whole number of di clock (tdiclk) only. the ipp_data can not be moved relative to the local start point. 4.7.8.5.2 lcd interface functional description figure 53 depicts the lcd interface timing for a generic ac tive matrix color tft panel. in this figure signals are shown with negative polarity. the sequence of events for active matrix interface timing is: ? di_clk internal di clock, used for calculation of other controls. ? ipp_disp_clk latches data into the panel on its ne gative edge (when positive polarity is selected). in active mode, ipp_disp_clk runs continuously. ? hsync causes the panel to start a new line. (usually ipp_pin_2 is used as hsync) ? vsync causes the panel to start a new frame. it always encompasses at least one hsync pulse. (usually ipp_pin_3 is used as vsync) ? drdy acts like an output enable signal to the crt display. this output enables the data to be shifted onto the display. when disabled, the data is invalid and the trace is off. (for drdy can be used either synchronous or asynchronous generic purpose pin as well.) figure 53. interface timing diagram for tft (active matrix) panels 4.7.8.5.3 tft panel sync pulse timing diagrams figure 54 depicts the horizontal timing (timing of one line) , including both the horizontal sync pulse and the data. all shown on the figure parameters are pr ogrammable. all controls are started by corresponding 123 m m-1 hsync vsync hsync line 1 line 2 line 3 line 4 line n-1 line n drdy ipp_disp_clk ipp_data
electrical characteristics i.mx51 applications processors for consumer and industrial products, rev. 6 freescale semiconductor 93 internal events?local start points. the timing diagrams correspond to inverse polarity of the ipp_disp_clk signal and active-low polarity of the hsync, vsync and drdy signals. figure 54. tft panels timing diagram?horizontal sync pulse figure 55 depicts the vertical timing (timing of one frame). all parameters shown in the figure are programmable. figure 55. tft panels timing diagram?vertical sync pulse di clock vsync hsync drdy d0 d1 ip5o ip13o ip9o ip8o ip8 ip9 dn ip10 ip7 ip5 ip6 local start point local start point local start point ipp_disp_clk ipp_data ip14 vsync hsync drdy start of frame end of frame ip12 ip15 ip13 ip11
i.mx51 applications processors for consumer and industrial products, rev. 6 94 freescale semiconductor electrical characteristics table 80 shows timing characteristics of signals presented in figure 54 and figure 55 . table 80. synchronous display interface timing characteristics (pixel level) id parameter symbol value description unit ip5 display interface clock period tdicp ( 1 ) display interface clock. ipp_disp_clk ns ip6 display pixel clock period tdpcp disp_clk_per_pixel tdicp time of translation of one pixel to display, disp_clk_per_pixel?number of pixel components in one pixel (1.n). the disp_clk_per_pixel is virtual parameter to define display pixel clock period. the disp_clk_per_pixel is received by dc/di one access division to n components. ns ip7 screen width time tsw (screen_width) tdicp screen_width?screen width in, interface clocks. horizontal blanking included. the screen_width should be built by suitable di?s counter 2 . ns ip8 hsync width time thsw (hsync_width) hsync_width?hsync width in di_clk with 0.5 di_clk resolution. defined by di?s counter. ns ip9 horizontal blank interval 1 thbi1 bgxp tdicp bgxp?width of a horizontal blanking before a first active data in a line. (in interface clocks). the bgxp should be built by suitable di?s counter. ns ip10 horizontal blank interval 2 thbi2 (screen_width - bgxp - fw) tdicp width a horizontal blanking after a last active data in a line. (in interface clocks) fw?with of active line in interface clocks. the fw should be built by suitable di?s counter. ns ip12 screen height tsh (screen_height) tsw screen_height? screen height in lines with blanking the screen_height is a distance between 2 vsyncs. the screen_height should be built by suitable di?s counter. ns ip13 vsync width tvsw vsync_width vsync_width?vsync width in di_clk with 0.5 di_clk resolution. defined by di?s counter ns ip14 vertical blank interval 1 tvbi1 bgyp tsw bgyp?width of first vertical blanking interval in line.the bgyp should be built by suitable di?s counter. ns ip15 vertical blank interval 2 tvbi2 (screen_height - bgyp - fh) tsw width of second vertical blanking interval in line.the fh should be built by suitable di?s counter. ns
electrical characteristics i.mx51 applications processors for consumer and industrial products, rev. 6 freescale semiconductor 95 the maximal accuracy of up/down edge of controls is ip5o offset of ipp_disp_clk todicp disp_clk_offset tdiclk disp_clk_offset? offset of ipp_disp_clk edges from local start point, in di_clk 2 (0.5 di_clk resolution) defined by disp_clk counter ns ip13o offset of vsync tovs vsync_offset tdiclk vsync_offset?offset of vsync edges from a local start point, when a vsync should be active, in di_clk 2 (0.5 di_clk resolution).the vsync_offset should be built by suitable di?s counter. ns ip8o offset of hsync tohs hsync_offset tdiclk hsync_offset?offset of hsync edges from a local start point, when a hsync should be active, in di_clk 2 (0.5 di_clk resolution).the hsync_offset should be built by suitable di?s counter. ns ip9o offset of drdy todrdy drdy_offset tdiclk drdy_offset? offset of drdy edges from a suitable local start point, when a corresponding data has been set on the bus, in di_clk 2 (0.5 di_clk resolution) the drdy_offset should be built by suitable di?s counter. ns 1 display interface clock period immediate value. disp_clk_period?number of di_clk per one tdicp. resolution 1/16 of di_clk di_clk_period?relation of between programing clock frequency and current system clock frequency display interface clock period average value. 2 di?s counter can define offset, period and up/down characteristic of output signal according to programed parameters of the counter. same of parameters in the table are not defined by di?s registers directly (by name), but can be generated by corresponding di?s counter. the screen_width is an input value for di?s hsync generation counter. the distance between hsyncs is a screen_width. table 80. synchronous display interface timing characteristics (pixel level) (continued) id parameter symbol value description unit tdicp t diclk disp_clk_period di_clk_period ------------------------------------------------------ - for integer disp_clk_period di_clk_period ------------------------------------------------------ - , t diclk floor disp_clk_period di_clk_period ------------------------------------------------------ - 0.5 0.5 + ?? ?? for fractional disp_clk_period di_clk_period ------------------------------------------------------ - , ? ? ? ? ? ? ? = tdicp t diclk disp_clk_period di_clk_period ------------------------------------------------------ - = accuracy 0.5 t diclk () 0.75ns =
i.mx51 applications processors for consumer and industrial products, rev. 6 96 freescale semiconductor electrical characteristics the maximal accuracy of up/down edge of ipp_data is the disp_clk_period, di_clk_period parameters are programmed via registers. figure 56 shows the synchronous display interface timing diagram for access level. the disp_clk_down and disp_clk_up parameters are set by using the register. table 81 shows the timing characteristics for the diagram shown in figure 56 . figure 56. synchronous display interface timing diagram?access level table 81. synchronous display interface timing characteristics (access level) id parameter symbol min typ 1 1 the exact conditions have not been finalized, but will likely match the current customer requirement for their specific display . these conditions may be chip specific. max unit ip16 display interface clock low time tckl tdicd-tdicu?1.5 tdicd 2 ?tdicu 3 tdicd?tdicu+1.5 ns ip17 display interface clock high time tckh tdicp?tdicd+tdicu?1.5 tdicp?tdicd+tdicu tdicp?tdicd+tdicu+1.5 ns ip18 data setup time tdsu tdicd?1.5 tdicu ? ns ip19 data holdup time tdhd tdicp?tdicd?1.5 tdicp?tdicu ? ns ip20o control signals offset times (defines for each pin) tocsu tocsu?1.5 tocsu tocsu+1.5 ? ip20 control signals setup time to display interface clock (defines for each pin) tcsu tdicd?1.5?tocsu%tdicp tdicu ? ns accuracy t diclk 0.75ns = ip19 ip18 ip20 vsync ip17 ip16 drdy hsync other controls ip20o local start point tdicd tdicu ipp_disp_clk ipp_data
electrical characteristics i.mx51 applications processors for consumer and industrial products, rev. 6 freescale semiconductor 97 4.7.8.6 interface to a tv encoder the interface has an 8-bit data bus, transferring a single 8-bit value (y/u/v) in each cycle. the timing of the interface is described in figure 57 . note ? the frequency of the clock disp_clk is 27 mhz (within 10%) ? the hsync, vsync signals are active low. ? the drdy signal is shown as active high. ? the transition to the next row is marked by the negative edge of the hsync signal. it remains low for a single clock cycle ? the transition to the next field/frame is marked by the negative edge of the vsync signal. it remains low for at least one clock cycles ? at a transition to an odd field (of the next frame), the negative edges of vsync and hsync coincide. ? at a transition is to an even field (of the same frame), they do not coincide. ? the active intervals?during which data is transferred?are marked by the hsync signal being high. 2 display interface clock down time 3 display interface clock up time where ceil(x) rounds the elements of x to the nearest integers towards infinity. tdicd 1 2 -- -t diclk ceil 2 disp_clk_down di_clk_period ------------------------------------------------------------- ?? ?? = tdicu 1 2 -- -t diclk ceil 2 disp_clk_up di_clk_period -------------------------------------------------- - ?? ?? =
i.mx51 applications processors for consumer and industrial products, rev. 6 98 freescale semiconductor electrical characteristics figure 57. tv encoder interface timing diagram hsync vsync cb y cr cb y cr y pixel data timing line and field timing - ntsc even field odd field odd field even field 624 621 311 308 line and field timing - pal hsync drdy vsync hsync drdy vsync even field odd field odd field even field 1 523 262 261 drdy hsync drdy vsync hsync vsync 524 525 2 3 4 10 263 264 265 266 267 268 269 273 622 623 625 1 2 23 309 310 312 313 314 336 56 34 316 315 drdy disp_clk ipp_data
electrical characteristics i.mx51 applications processors for consumer and industrial products, rev. 6 freescale semiconductor 99 4.7.8.6.1 tv encoder performance specifications all the parameters in the table ar e defined under the following conditions: rset = 1.05 k 1%, resistor on vrefout pin to ground rload = 37.5 1%, output load to ground the tv encoder output specifications are shown in table 82 . table 82. tv encoder video performance specifications parameter conditions min typ max unit dac static performance resolution 1 ?? 1 0 ? b i t s integral nonlinearity (inl) 2 ? ? 1 2 lsbs differential nonlinearity (dnl) 2 ? ? 0.6 1 lsbs channel-to-channel gain matching 2 ?? 2 ? % full scale output voltage 2 rset = 1.05 k 1% rload = 37.5 1% 1.24 1.35 1.45 v dac dynamic performance spurious free dynamic range (sfdr) f out = 3.38 mhz f samp = 216 mhz ?5 9?d b c spurious free dynamic range (sfdr) f out = 9.28 mhz f samp = 297 mhz ?5 4?d b c video performance in sd mode 2, 3 short term jitter (line to line) ? ? 2.5 ? ns long term jitter (field to field) ? ? 3.5 ? ns frequency response 0-4.0 mhz ?0.1 ? 0.1 db 5.75 mhz ?0.7 ? 0 db luminance nonlinearity ? ? 0.5 ? % differential gain ? ? 0.35 ? % differential phase ? ? 0.6 ? degrees signal-to-noise ratio (snr) flat field full bandwidth ? 75 ? db hue accuracy ? ? 0.8 ? degrees color saturation accuracy ? ? 1.5 ? % chroma am noise ? ? ?70 ? db chroma pm noise ? ? ?47 ? db chroma nonlinear phase ? ? 0.5 ? degrees chroma nonlinear gain ? ? 2.5 ? % chroma/luma intermodulation ? ? 0.1 ? %
i.mx51 applications processors for consumer and industrial products, rev. 6 100 freescale semiconductor electrical characteristics 4.7.8.7 asynchronous interfaces 4.7.8.7.1 standard parallel interfaces the ipu has four signal generator machines for asynchronous signal. each machine generates ipu?s internal control levels (0 or 1) by up and down are defined in registers. each asynchronous pin has a dynamic connection with one of the signal generators. this connection is redefined again with a new display access (pixel/component) the ipu can genera te control signals according to system 80/68 requirements. the burst length is received as a result from predefined behavior of the internal signal generator machines. the access to a display is realized by the following: ? cs (ipp_cs) chip select ? wr (ipp_pin_11) write strobe ? rd (ipp_pin_12) read strobe ? rs (ipp_pin_13) register select (a0) both system 80 and system 68k interfaces are suppor ted for all described modes as depicted in figure 58 , figure 59 , figure 60 , and figure 61 . the timing images correspond to active-low ipp_cs, wr and rd signals. each asynchronous access is defined by an access size pa rameter. this parameter can be different between different kinds of accesses. this parameter defines a length of windows, when suitable controls of the current access are valid. a pause between two different display accesses can be guaranteed by programing of suitable access sizes. there are no minimal/maximal hold/setup time hard defined by di. each control signal can be switched at any time during access size. chroma/luma gain inequality ? ? 1.0 ? % chroma/luma delay inequality ? ? 1.0 ? ns ? ???? video performance in hd mode 2 luma frequency response 0-30 mhz ?0.2 ? 0.2 db chroma frequency response 0-15 mhz, ycbcr 422 mode ?0.2 ? 0.2 db luma nonlinearity ? ? 3.2 ? % chroma nonlinearity ? ? 3.4 ? % luma signal-to-noise ratio 0-30 mhz ? 62 ? db chroma signal-to-noise ratio 0-15 mhz ? 72 ? db 1 guaranteed by design 2 guaranteed by characterization 3 r set = vrefout's external resistor to ground = 1.05 k table 82. tv encoder video performance specifications (continued)
electrical characteristics i.mx51 applications processors for consumer and industrial products, rev. 6 freescale semiconductor 101 figure 58. asynchronous parallel system 80 interface (type 1) timing diagram rs wr rd rs wr rd burst access mode with sampling by cs signal single access mode (all control signals are not active for one display interface clock after each display access) ipp_cs ipp_data ipp_cs ipp_data
i.mx51 applications processors for consumer and industrial products, rev. 6 102 freescale semiconductor electrical characteristics figure 59. asynchronous parallel system 80 interface (type 2) timing diagram rs wr rd rs wr rd burst access mode with sampling by wr/rd signals single access mode (all control signals are not active for one display interface clock after each display access) ipp_cs ipp_cs ipp_data ipp_data
electrical characteristics i.mx51 applications processors for consumer and industrial products, rev. 6 freescale semiconductor 103 figure 60. asynchronous parallel system 68k interface (type 1) timing diagram wr rd wr rd (read/write) (enable) rs rs (read/write) (enable) burst access mode with sampling by cs signal single access mode (all control signals are not active for one display interface clock after each display access) ipp_cs ipp_cs ipp_data ipp_data
i.mx51 applications processors for consumer and industrial products, rev. 6 104 freescale semiconductor electrical characteristics figure 61. asynchronous parallel system 68k interface (type 2) timing diagram display operation can be performed with ipp_wait signal. the di reacts to the incoming ipp_wait signal with 2 di_clk delay. the di finishes a current access and a next access is postponed until ipp_wait release. rs wr rd rs wr rd (read/write) (enable) (read/write) (enable) burst access mode with sampling by enable signal single access mode (all control signals are not active for one display interface clock after each display access) ipp_cs ipp_data ipp_cs ipp_data
electrical characteristics i.mx51 applications processors for consumer and industrial products, rev. 6 freescale semiconductor 105 figure 62 shows timing of the parallel interface with ipp_wait control. figure 62. parallel interface timing diagram?read wait states di clock ipp_data wr rd ipp_wait ipp_data_in waiting waiting ip39 ipp_cs
i.mx51 applications processors for consumer and industrial products, rev. 6 106 freescale semiconductor electrical characteristics 4.7.8.7.2 asynchronous parallel interface timing parameters figure 63 depicts timing of asynchronous parallel interf aces based on the system 80 and system 68k interfaces. table 84 shows the timing characteristics at display access level. table 83 shows the timing characteristics at the logical level?from configuration perspective. all timing diagrams are based on active low control signals (signals polarity is controlled through the di_disp_sig_pol register). figure 63. asynchronous parallel interface timing diagram table 83. asynchronous display interface timing parameters (pixel level) id parameter symbol value description unit ip27 read system cycle time tcycr access_size_# predefined value in di register ns ip28a address write system cycle time tcycwa access_size_# predefined value in di register ns ip28d data write system cycle time tcycwd access_size_# predefined value in di register ns ip29 rs start tdcsrr up# rs strobe switch, predefined value in di register ns ip30 cs start tdcsc up# cs strobe switch, predefined value in di register ns di clock rs wr rd a0 d0 d1 pp_data_in d2 d3 local start point ip27 ip28d ip28a local start point local start point local start point local start point ip37 ip33 ip35 ip38 ip34 ip36 ip29 ip31 ip32 ip47 ip30 ipp_cs ipp_data
electrical characteristics i.mx51 applications processors for consumer and industrial products, rev. 6 freescale semiconductor 107 ip31 cs hold tdchc down# cs strobe release, predefined value in di register ? ip32 rs hold tdchrr down# rs strobe release, predefined value in di register ? ip33 read start tdcsr up# read strobe switch, predefined value in di register ns ip34 read hold tdchr down# read strobe release signal, predefined value in di register ns ip35 write start tdcsw up# write strobe switch, predefined value in di register ns ip36 controls hold time for write tdchw down# write strobe release, predefined value in di register ns ip37 slave device data delay 1 tracc delay of incoming data physical delay of display?s data, defined from read access local start point ns ip38 slave device data hold time 3 troh hold time of data on the buss time that display read data is valid in input bus ns ip47 read time point 13 tdrp data sampling point point of input data sampling by di, predefined in dc microcode ? 1 this parameter is a requirement to the display connected to the ipu. table 84. asynchronous parallel interface timing parameters (access level) id parameter symbol min typ 1 max unit ip27 read system cycle time tcycr tdicpr?1.5 tdicpr 2 tdicpr+1.5 ns ip28 write system cycle time tcycw tdicpw?1.5 tdicpw 3 tdicpw+1.5 ns ip29 rs start tdcsrr tdicurs?1.5 tdicurs tdicurs+1.5 ns ip30 cs start tdcsc tdicucs?1.5 tdicur tdicucs+1.5 ns ip31 cs hold tdchc tdicdcstdicucs?1.5 tdicdcs 4 ?tdicucs 5 tdicdcs?tdicucs+1.5 ns ip32 rs hold tdchrr tdicdrs?tdicurs?1.5 tdicdrs 6 ?tdicurs 7 tdicdrs?tdicurs+1.5 ns ip33 controls setup time for read tdcsr tdicur?1.5 tdicur tdicur+1.5 ns ip34 controls hold time for read tdchr tdicdr?tdicur?1.5 tdicdr 8 ?tdicur 9 tdicdr?tdicur+1.5 ns ip35 controls setup time for write tdcsw tdicuw?1.5 tdicuw tdicuw+1.5 ns ip36 controls hold time for write tdchw tdicdw?tdicuw?1.5 tdicpw 10 ?tdicuw 11 tdicdw?tdicuw+1.5 ns ip37 slave device data delay 12 tracc 0 ? tdrp 13 ?tlbd 14 ?tdicur?1.5 ns ip38 slave device data hold time 8 troh tdrp?tlbd?tdicdr+1.5 ? tdicpr?tdicdr?1.5 ns table 83. asynchronous display interface timing parameters (pixel level) (continued) id parameter symbol value description unit
i.mx51 applications processors for consumer and industrial products, rev. 6 108 freescale semiconductor electrical characteristics ip39 setup time for wait signal tswait ? ? ? ? ip47 read time point 13 tdrp tdrp?1.5 tdrp tdrp+1.5 ns 1 the exact conditions have not been finalized, but will likely match the current customer requirement for their specific display . these conditions may be chip specific. 2 display period value for read access_size is predefined in register 3 display period value for write access_size is predefined in register 4 display control down for cs disp_down is predefined in register 5 display control up for cs disp_up is predefined in register 6 display control down for rs disp_down is predefined in register 7 display control up for rs disp_up is predefined in register 8 display control down for read disp_down is predefined in register table 84. asynchronous parallel interface timing parameters (access level) (continued) id parameter symbol min typ 1 max unit tdicpr t di_clk ceil di_access_size_# di_clk_period -------------------------------------------------------- - = tdicpw t di_clk ceil di_access_size_# di_clk_period -------------------------------------------------------- - = tdicdcs 1 2 -- -t di_clk ceil 2 disp_down_# di_clk_period ---------------------------------------------------- - ?? ?? = tdicucs 1 2 -- -t di_clk ceil 2 disp_up_# di_clk_period ---------------------------------------------- - ?? ?? = tdicdrs 1 2 -- -t di_clk ceil 2 disp_down_# di_clk_period ---------------------------------------------------- - ?? ?? = tdicurs 1 2 -- -t di_clk ceil 2 disp_up_# di_clk_period ---------------------------------------------- - ?? ?? = tdicdr 1 2 -- -t di_clk ceil 2 disp_down_# di_clk_period ---------------------------------------------------- - ?? ?? =
electrical characteristics i.mx51 applications processors for consumer and industrial products, rev. 6 freescale semiconductor 109 4.7.8.8 standard serial interfaces the ipu supports the following types of asynchronous serial interfaces: 1. 3-wire (with bidirectional data line). 2. 4-wire (with separate data input and output lines). 3. 5-wire type 1 (with sampling rs by the serial clock). 4. 5-wire type 2 (with sampling rs by the chip select signal). the ipu has four independent outputs and one input. the por t can be configured to provide 3, 4, or 5-wire interfaces. figure 64 depicts the timing diagram of the 3-wire serial interface. the timing diagrams correspond to active-low ipp#_cs signal and the straight polarity of the ipp_clk signal. for this interface, a bidirectional data line is used outside the chip. the ipu still uses separate input and output data lines (ipp_ind_dispb_sd_d and ipp_do_dispb_sd_d). the i/o mux should provide 9 display control up for read disp_up is predefined in register 10 display control down for read disp_down is predefined in register 11 display control up for write disp_up is predefined in register 12 this parameter is a requirement to the display connected to the ipu 13 data read point note: disp#_read_en?operand of dc?s microcde read command to sample incoming data 14 loop back delay tlbd is the cumulative propagation delay of read controls and read data. it includes an ipu output delay, a chip-level output delay, board delays, a chip-level input delay, an ipu input delay. this value is chip specific. tdicur 1 2 -- -t di_clk ceil 2 disp_up_# di_clk_period ---------------------------------------------- - ?? ?? = tdicdrw 1 2 -- -t di_clk ceil 2 disp_down_# di_clk_period ---------------------------------------------------- - ?? ?? = tdicuw 1 2 -- -t di_clk ceil 2 disp_up_# di_clk_period ---------------------------------------------- - ?? ?? = tdrp t di_clk ceil disp#_read_en di_clk_period ------------------------------------------------ - =
i.mx51 applications processors for consumer and industrial products, rev. 6 110 freescale semiconductor electrical characteristics joining the internal data lines to the bidirectional external line according to the ipp_obe_dispb_sd_d signal provided by the ipu. figure 64. 3-wire serial interface timing diagram figure 65 depicts timing diagram of the 4-wire serial inte rface. for this interface, there are separate input and output data lines both inside and outside the chip. figure 65. 4-wire serial interface timing diagram preamble dispb_d#_cs dispb_sd_d_clk dispb_sd_d rw rs input or output data d7 d6 d5 d4 d3 d2 d1 d0 programed delay programed delay preamble dispb_d#_cs dispb_sd_d_clk dispb_sd_d rw rs output data d7 d6 d5 d4 d3 d2 d1 d0 dispb_sd_d (output) (input) preamble dispb_d#_cs dispb_sd_d_clk dispb_sd_d rw rs input data dispb_sd_d d7 d6 d5 d4 d3 d2 d1 d0 (output) (input) write read programed delay programed delay programed delay programed delay
electrical characteristics i.mx51 applications processors for consumer and industrial products, rev. 6 freescale semiconductor 111 figure 66 depicts timing of the 5-wire serial interface. for this interface, a separate rs line is added. figure 66. 5-wire serial interface timing diagram preamble dispb_d#_cs dispb_sd_d_clk dispb_sd_d rw output data d7 d6 d5 d4 d3 d2 d1 d0 dispb_sd_d (output) (input) preamble dispb_d#_cs dispb_sd_d_clk dispb_sd_d rw input data dispb_sd_d d7 d6 d5 d4 d3 d2 d1 d0 (output) (input) write read dispb_ser_rs dispb_ser_rs programed delay programed delay programed delay programed delay programed delay programed delay
i.mx51 applications processors for consumer and industrial products, rev. 6 112 freescale semiconductor electrical characteristics 4.7.8.8.1 asynchronous serial interface timing parameters figure 67 depicts timing of the serial interface. table 85 shows timing characteristics at display access level. figure 67. asynchronous serial interface timing diagram table 85. asynchronous serial interface timing characteristics (access level) id parameter symbol min typ 1 max unit ip48 read system cycle time tcycr tdicpr?1.5 tdicpr 2 tdicpr+1.5 ns ip49 write system cycle time tcycw tdicpw?1.5 tdicpw 3 tdicpw+1.5 ns ip50 read clock low pulse width trl tdicdr?tdicur?1.5 tdicdr 4 ?tdicur 5 tdicdr?tdicur+1.5 ns ip51 read clock high pulse width trh tdicpr?tdicdr+tdicur?1.5 tdicpr?tdicdr+ tdicur tdicpr?tdicdr+tdicur+ 1.5 ns di clock ipp_dispb_do_sd_d ipp_do_dispb_ser_cs ipp_do_dispb_ser_rs ipp_do_dispb_sd_d_clk ipp_ind_dispb_sd_d local start point ip68 ip48, ip49, ip62, ip63 ip51,53 ip55, ip57, ip54, ip56, ip65, ip67 ip60, ip58 ip59 ip50, ip52 ip64, ip66 ip61 ip69 ip70 ip71 ip72 ip73
electrical characteristics i.mx51 applications processors for consumer and industrial products, rev. 6 freescale semiconductor 113 ip52 write clock low pulse width twl tdicdw?tdicuw?1.5 tdicdw 6 ?tdicuw 7 tdicdw?tdicuw+1.5 ns ip53 write clock high pulse width twh tdicpw?tdicdw+ tdicuw?1.5 tdicpw?tdicdw+ tdicuw tdicpw?tdicdw+ tdicuw+1.5 ns ip54 controls setup time for read tdcsr tdicur?1.5 tdicur ? ns ip55 controls hold time for read tdchr tdicpr?tdicdr?1.5 tdicpr?tdicdr ? ns ip56 controls setup time for write tdcsw tdicuw?1.5 tdicuw ? ns ip57 controls hold time for write tdchw tdicpw?tdicdw?1.5 tdicpw?tdicdw ? ns ip58 slave device data delay 8 tracc 0 ? tdrp 9 ?tlbd 10 -tdicur-1.5 ns ip59 slave device data hold time 8 troh tdrp-tlbd-tdicdr+1.5 ? tdicpr-tdicdr-1.5 ns ip60 write data setup time tds tdicdw-1.5 tdicdw ? ns ip61 write data hold time tdh tdicpw-tdicdw-1.5 tdicpw-tdicdw ? ns ip62 read period 2 tdicpr tdicpr-1.5 tdicpr tdicpr+1.5 ns ip63 write period 3 tdicpw tdicpw-1.5 tdicpw tdicpw+1.5 ns ip64 read down time 4 tdicdr tdicdr-1.5 tdicdr tdicdr+1.5 ns ip65 read up time 5 tdicur tdicur-1.5 tdicur tdicur+1.5 ns ip66 write down time 6 tdicdw tdicdw-1.5 tdicdw tdicdw+1.5 ns ip67 write up time 7 tdicuw tdicuw-1.5 tdicuw tdicuw+1.5 ns ip68 read time point 9 tdrp tdrp-1.5 tdrp tdrp+1.5 ns ip69 clock offset 11 toclk toclk-1.5 toclk toclk+1.5 ns ip70 rs up time 12 tdicurs tdicurs?1.5 tdicurs tdicurs+1.5 ns ip71 rs down time 13 tdicdrs tdicdrs -1.5 tdicdrs tdicdrs+1.5 ns ip72 cs up time 14 tdicucs tdicucs ?1.5 tdicucs tdicucs+1.5 ns ip73 cs down time 15 tdicdcs tdicdcs ?1.5 tdicdcs tdicdcs+1.5 ns 1 the exact conditions have not been finalized, but will likely match the current customer requirement for their specific display . these conditions may be chip specific. 2 display interface clock period value for read 3 display interface clock period value for write table 85. asynchronous serial interface timing characteristics (access level) (continued) id parameter symbol min typ 1 max unit tdicpr t di_clk ceil disp#_if_clk_per_rd di_clk_period -------------------------------------------------------------------- = tdicpw t di_clk ceil disp#_if_clk_per_wr di_clk_period --------------------------------------------------------------------- - =
i.mx51 applications processors for consumer and industrial products, rev. 6 114 freescale semiconductor electrical characteristics 4 display interface clock down time for read 5 display interface clock up time for read 6 display interface clock down time for write 7 display interface clock up time for write 8 this parameter is a requirement to the display connected to the ipu 9 data read point disp_rd_en is predefined in register 10 loop back delay tlbd is the cumulative propagation delay of read controls and read data. it includes an ipu output delay, a chip-level output delay, board delays, a chip-level input delay, an ipu input delay. this value is chip specific. 11 display interface clock offset value clk_offset is predefined in register 12 display rs up time disp_rs_up is predefined in register 13 display rs down time disp_rs_down is predefined in register 14 display rs up time disp_cs_up is predefined in register tdicdr 1 2 -- -t di_clk ceil 2 disp_down_# di_clk_period ---------------------------------------------------- - ?? ?? = tdicur 1 2 -- -t di_clk ceil 2 disp_up_# di_clk_period ---------------------------------------------- - ?? ?? = tdicdw 1 2 -- -t di_clk ceil 2 disp_down_# di_clk_period ---------------------------------------------------- - ?? ?? = tdicuw 1 2 -- -t di_clk ceil 2 disp_up_# di_clk_period ---------------------------------------------- - ?? ?? = tdrp t di_clk ceil disp_read_en di_clk_period ---------------------------------------------- - = toclk t di_clk ceil disp_clk_offset di_clk_period ------------------------------------------------------- - = tdicurs t di_clk ceil disp_rs_up_# di_clk_period ---------------------------------------------- - = tdicdrs t di_clk ceil disp_rs_down_# di_clk_period ------------------------------------------------------ = tdicucs t di_clk ceil disp_cs_up_# di_clk_period ---------------------------------------------- - =
electrical characteristics i.mx51 applications processors for consumer and industrial products, rev. 6 freescale semiconductor 115 4.7.9 1-wire timing parameters figure 68 depicts the rpp timing and table 86 lists the rpp timing parameters. figure 68. reset and presence pulses (rpp) timing diagram figure 69 depicts write 0 sequence timing, and table 87 lists the timing parameters. figure 69. write 0 sequence timing diagram 15 display rs down time disp_cs_down is predefined in register. table 86. rpp sequence delay comparisons timing parameters id parameters symbol min typ max unit ow1 reset time low t rstl 480 511 ? s ow2 presence detect high t pdh 15 ? 60 s ow3 presence detect low t pdl 60 ? 240 s ow4 reset time high t rsth 480 512 ? s table 87. wr0 sequence timing parameters id parameter symbol min typ max unit ow5 write 0 low time t wr0_low 60 100 120 s ow6 transmission time slot t slot ow5 117 120 s tdicdcs t di_clk ceil () disp_cs_down_# di_clk_period ------------------------------------------------------ = one-wire bus ds2502 tx ?presence pulse? (batt_line) 1-wire tx ?reset pulse? ow1 ow2 ow3 ow4 ow5 ow6 one-wire bus (batt_line)
i.mx51 applications processors for consumer and industrial products, rev. 6 116 freescale semiconductor electrical characteristics figure 70 depicts write 1 sequence timing, figure 71 depicts the read sequence timing, and table 88 lists the timing parameters. figure 70. write 1 sequence timing diagram figure 71. read sequence timing diagram 4.7.10 pulse width modulator (pwm) timing parameters this section describes the electrical information of the pwm.the pwm can be programmed to select one of three clock signals as its source frequency. the selected clock signal is passed through a prescaler before being input to the counter. the output is available at the pulse-width modulator output (pwmo) external pin. table 88. wr1 /rd timing parameters id parameter symbol min typ max unit ow7 write /read low time t low1 1 5 15 s ow8 transmission time slot t slot 60 117 120 s ow9 release time t release 15 ? 45 s ow7 ow8 one-wire bus (batt_line) ow7 ow8 ow9 one-wire bus (batt_line)
electrical characteristics i.mx51 applications processors for consumer and industrial products, rev. 6 freescale semiconductor 117 figure 72 depicts the timing of the pwm, and table 89 lists the pwm timing parameters. figure 72. pwm timing 4.7.11 p-ata timing parameters this section describes the timing pa rameters of the parallel ata module which are compliant with ata/atapi-5 specification. parallel ata module can work on pio/multi-word dma/ultra dma transfer modes. each transfer mode has different data transfer rate, ultra dma mode 4 data transfer rate is up to 66 mbyte/s. parallel ata module interface consist of a total of 29 pins, some pins act on different function in different transfer mode. there are different requirements of timing re lationships among the function pins conform with ata/atapi-5 specification and these requirements ar e configurable by the ata module registers. table 89. pwm output timing parameter ref. no. parameter min max unit 1 system clk frequency 1 1 cl of pwmo = 30 pf 0 ipg_clk mhz 2a clock high time 12.29 ? ns 2b clock low time 9.91 ? ns 3a clock fall time ? 0.5 ns 3b clock rise time ? 0.5 ns 4a output delay time ? 9.37 ns 4b output setup time 8.71 ? ns system clock 2a 1 pwm output 3b 2b 3a 4b 4a
i.mx51 applications processors for consumer and industrial products, rev. 6 118 freescale semiconductor electrical characteristics table 90 and figure 73 define the ac characteristics of all the p-ata interface signals on all data transfer modes. figure 73. p-ata interface signals timing diagram the user needs to use level shifters for 5.0 v compatibility on the ata interface. the i.mx51 p-ata interface is 3.3 v compatible. the use of bus buffers introduces delay on the bus and introduces skew between signal lines. these factors make it difficult to operate the bus at the highest speed (udma-4) when bus buffers are used. if fast udma mode operation is needed, this may not be compatible with bus buffers. another area of attention is the slew rate limit imposed by the ata specification on the ata bus. according to this limit, any signal driven on the bus s hould have a slew rate between 0.4 and 1.2 v/ns with a 40 pf load. not many vendors of bus buffers specify slew rate of the outgoing signals. when bus buffers are used, the ata_data bus buffer is special. this is a bidirectional bus buffer, so a direction control signal is needed. this direction c ontrol signal is ata_buffer_en. when its high, the bus should drive from host to device. when its low, the bus should drive from device to host. steering of the signal is such that contention on the host a nd device tri-state busses is always avoided. in the timing equations, some timing parameters are used. these parameters depend on the implementation of the i.mx51 p-ata interface on silicon, the bus buffer used, the cable delay and cable skew. table 90. ac characteristics of all interface signals id parameter symbol min max unit si1 rising edge slew rate for any signal on ata interface. 1 1 srise and sfall shall meet this requirement when measured at the sender?s connector from 10?90% of full signal amplitude with all capacitive loads from 15 ? 40 pf where all signals have the same capacitive load value. s rise ? 1.25 v/ns si2 falling edge slew rate for any signal on ata interface (see note) s fall ? 1.25 v/ns si3 host interface signal capacitance at the host connector c host ?20pf ata interface signals si1 si2
electrical characteristics i.mx51 applications processors for consumer and industrial products, rev. 6 freescale semiconductor 119 table 91 shows ata timing parameters. table 91. p-ata timing parameters name description value/ contributing factor 1 1 values provided where applicable. t bus clock period (ipg_clk_ata) peripheral clock frequency ti_ds set-up time ata_data to ata_iordy edge (udma-in only) udma0 udma1 udma2, udma3 udma4 15 ns 10 ns 7 ns 5 ns ti_dh hold time ata_iordy edge to ata_data (udma-in only) udma0, udma1, udma2, udma3, udma4 5.0 ns tco propagation delay bus clock l-to-h to ata_cs0, ata_cs1, ata_da2, ata_da1, ata_da0, ata_dior, ata_diow, ata_dmack, ata_data, ata_buffer_en 12.0 ns tsu set-up time ata_data to bus clock l-to-h 8.5 ns tsui set-up time ata_iordy to bus clock h-to-l 8.5 ns thi hold time ata_iordy to bus clock h to l 2.5 ns tskew1 max difference in propagation delay bus clock l-to-h to any of following signals ata_cs0, ata_cs1, ata_da2, ata_da1, ata_da0, ata_dior, ata_diow, ata_dmack, ata_data (write), ata_buffer_en 7ns tskew2 max difference in buffer propagation delay for any of following signals ata_cs0, ata_cs1, ata_da2, ata_da1, ata_da0, ata_dior, ata_diow, ata_dmack, ata_data (write), ata_buffer_en transceiver tskew3 max difference in buffer propagation delay for any of following signals ata_iordy, ata_data (read) transceiver tbuf max buffer propagation delay transceiver tcable1 cable propagation delay for ata_data cable tcable2 cable propagation delay for control signals ata_dior, ata_diow, ata_iordy, ata_dmack cable tskew4 max difference in cable propagation delay between ata_iordy and ata_data (read) cable tskew5 max difference in cable propagation delay between (ata_dior, ata_diow, ata_dmack) and ata_cs0, ata_cs1, ata_da2, ata_da1, ata_da0, ata_data(write) cable tskew6 max difference in cable propagation delay without accounting for ground bounce cable
i.mx51 applications processors for consumer and industrial products, rev. 6 120 freescale semiconductor electrical characteristics 4.7.11.1 pio mode read timing figure 74 shows timing for pio read and table 92 lists the timing parameters for pio read. figure 74. pio read timing diagram table 92. pio read timing parameters ata parameter parameter from figure 74 value controlling variable t1 t1 t1 (min) = time_1 t ? (tskew1 + tskew2 + tskew5) time_1 t2 t2r t2 min) = time_2r t ? (tskew1 + tskew2 + tskew5) time_2r t9 t9 t9 (min) = time_9 t ? (tskew1 + tskew2 + tskew6) time_3 t5 t5 t5 (min) = tco + tsu + tbuf + tbuf + tcable1 + tcable2 if not met, increase time_2 t6 t6 0 ? ta ta ta (min) = (1.5 + time_ax) t ? (tco + tsui + tcable2 + tcable2 + 2 tbuf) time_ax trd trd1 trd1 (max) = (?trd) + (tskew3 + tskew4) trd1 (min) = (time_pio_rdx ? 0.5) t ? (tsu + thi) (time_pio_rdx ? 0.5) t > tsu + thi + tskew3 + tskew4 time_pio_rdx t0 ? t0 (min) = (time_1 + time_2 + time_9) t time_1, time_2r, time_9
electrical characteristics i.mx51 applications processors for consumer and industrial products, rev. 6 freescale semiconductor 121 figure 75 shows timing for pio write and table 93 lists the timing parameters for pio write. figure 75. multi-word dma (mdma) timing table 93. pio write timing parameters ata parameter parameter from figure 75 value controlling variable t1 t1 t1 (min) = time_1 t ? (tskew1 + tskew2 + tskew5) time_1 t2 t2w t2 (min) = time_2w t ? (tskew1 + tskew2 + tskew5) time_2w t9 t9 t9 (min) = time_9 t ? (tskew1 + tskew2 + tskew6) time_9 t3 ? t3 (min) = (time_2w ? time_on) t ? (tskew1 + tskew2 +tskew5) if not met, increase time_2w t4 t4 t4 (min) = time_4 t ? tskew1 time_4 ta ta ta = (1.5 + time_ax) t ? (tco + tsui + tcable2 + tcable2 + 2 tbuf) time_ax t0 ? t0(min) = (time_1 + time_2 + time_9) t time_1, time_2r, time_9 ? ? avoid bus contention when switching buffer on by making ton long enough ? ? ? avoid bus contention when switching buffer off by making toff long enough ?
i.mx51 applications processors for consumer and industrial products, rev. 6 122 freescale semiconductor electrical characteristics figure 76 shows timing for mdma read, figure 77 shows timing for mdma write, and table 94 lists the timing parameters for mdma read and write. figure 76. mdma read timing diagram figure 77. mdma write timing diagram table 94. mdma read and write timing parameters ata parameter parameter from figure 76 , figure 77 value controlling variable tm, ti tm tm (min) = ti (min) = time_m t ? (tskew1 + tskew2 + tskew5) time_m td td, td1 td1.(min) = td (min) = time_d t ? (tskew1 + tskew2 + tskew6) time_d tk tk tk.(min) = time_k t ? (tskew1 + tskew2 + tskew6) time_k t0 ? t0 (min) = (time_d + time_k) t time_d, time_k tg(read) tgr tgr (min-read) = tco + tsu + tbuf + tbuf + tcable1 + tcable2 tgr.(min-drive) = td ? te(drive) time_d tf(read) tfr tfr (min-drive) = 0 ? tg(write) ? tg (min-write) = time_d t ? (tskew1 + tskew2 + tskew5) time_d tf(write) ? tf (min-write) = time_k t ? (tskew1 + tskew2 + tskew6) time_k tl ? tl (max) = (time_d + time_k?2) t ? (tsu + tco + 2 tbuf + 2 tcable2) time_d, time_k
electrical characteristics i.mx51 applications processors for consumer and industrial products, rev. 6 freescale semiconductor 123 4.7.11.2 ultra dma (udma) input timing figure 78 shows timing when the udma in transfer starts, figure 79 shows timing when the udma in host terminates transfer, figure 80 shows timing when the udma in device terminates transfer, and table 95 lists the timing parameters for udma in burst. figure 78. udma in transfer starts timing diagram figure 79. udma in host terminates transfer timing diagram tn, tj tkjn tn= tj= tkjn = (max(time_k,. time_jn) t ? (tskew1 + tskew2 + tskew6) time_jn ?t o n toff ton = time_on t ? tskew1 toff = time_off t ? tskew1 ? table 94. mdma read and write timing parameters (continued) ata parameter parameter from figure 76 , figure 77 value controlling variable
i.mx51 applications processors for consumer and industrial products, rev. 6 124 freescale semiconductor electrical characteristics figure 80. udma in device terminates transfer timing diagram table 95. udma in burst timing parameters ata parameter parameter from figure 78 , figure 79 , figure 80 description controlling variable tack tack tack (min) = (time_ack t) ? (tskew1 + tskew2) time_ack tenv tenv tenv (min) = (time_env t) ? (tskew1 + tskew2) tenv (max) = (time_env t) + (tskew1 + tskew2) time_env tds tds1 tds ? (tskew3) ? ti_ds > 0 tskew3, ti_ds, ti_dh should be low enough tdh tdh1 tdh ? (tskew3) ? ti_dh > 0 tcyc tc1 (tcyc ? tskew) > t t big enough trp trp trp (min) = time_rp t ? (tskew1 + tskew2 + tskew6) time_rp ?t x 1 1 1 there is a special timing requirement in the ata host that requires the internal diow to go only high 3 clocks after the last active edge on the dstrobe signal. the equation given on this line tries to capture this constraint. (time_rp t) ? (tco + tsu + 3t + 2 tbuf + 2 tcable2) > trfs (drive) time_rp tmli tmli1 tmli1 (min) = (time_mlix + 0.4) t time_mlix tzah tzah tzah (min) = (time_zah + 0.4) t time_zah tdzfs tdzfs tdzfs = (time_dzfs t) ? (tskew1 + tskew2) time_dzfs tcvh tcvh tcvh = (time_cvh t) ? (tskew1 + tskew2) time_cvh ?t o n toff 2 2 make ton and toff big enough to avoid bus contention. ton = time_on t ? tskew1 toff = time_off t ? tskew1 ?
electrical characteristics i.mx51 applications processors for consumer and industrial products, rev. 6 freescale semiconductor 125 4.7.11.3 udma output timing figure 81 shows timing when the udma out transfer starts, figure 82 shows timing when the udma out host terminates transfer, figure 83 shows timing when the udma out device terminates transfer, and table 96 lists the timing parameters for udma out burst. figure 81. udma out transfer starts timing diagram figure 82. udma out host terminates transfer timing diagram
i.mx51 applications processors for consumer and industrial products, rev. 6 126 freescale semiconductor electrical characteristics figure 83. udma out device terminates transfer timing diagram table 96. udma out burst timing parameters ata parameter parameter from figure 81 , figure 82 , figure 83 value controlling variable tack tack tack (min) = (time_ack t) ? (tskew1 + tskew2) time_ack tenv tenv tenv (min) = (time_env t) ? (tskew1 + tskew2) tenv (max) = (time_env t) + (tskew1 + tskew2) time_env tdvs tdvs tdvs = (time_dvs t) ? (tskew1 + tskew2) time_dvs tdvh tdvh tdvs = (time_dvh t) ? (tskew1 + tskew2) time_dvh tcyc tcyc tcyc = time_cyc t ? (tskew1 + tskew2) time_cyc t2cyc ? t2cyc = time_cyc 2 t time_cyc trfs1 trfs trfs = 1.6 t + tsui + tco + tbuf + tbuf ? ? tdzfs tdzfs = time_dzfs t ? (tskew1) time_dzfs tss tss tss = time_ss t ? (tskew1 + tskew2) time_ss tmli tdzfs_mli tdzfs_mli =max (time_dzfs, time_mli) t ? (tskew1 + tskew2) ? tli tli1 tli1 > 0 ? tli tli2 tli2 > 0 ? tli tli3 tli3 > 0 ? tcvh tcvh tcvh = (time_cvh t) ? (tskew1 + tskew2) time_cvh ?t o n toff ton = time_on t ? tskew1 toff = time_off t ? tskew1 ?
electrical characteristics i.mx51 applications processors for consumer and industrial products, rev. 6 freescale semiconductor 127 4.7.12 sim (subscriber identification module) timing this section describes the electrical parameters of the sim module. each sim module interface consists of 12 signals (two separate ports each containing si x signals). typically a a port uses five signals. the interface is designed to be used with synchronous sim cards meaning the sim module provides the clock used by the sim card. the clock frequency is typically 372 times the tx/rxdata rate, however the sim module can work with clk frequenc ies of 16 times the tx/rx data rate. there is no timing relationship between the clock and the data. the clock that the sim module provides to the sim card is used by the sim card to recover the clock from the data in the same manner as standard uart data exchanges. all six signals (5 for bi-dir ectional tx/rx) of the sim module are asynchronous to each other. there are no required timing relationships between signals in normal mode. the sim card is initiated by the interface device; the sim card responds with answer to reset. although the sim interface has no defined requirements, the iso-7816 defines reset and power-down sequences. (for detailed information, see iso-7816.) table 97 defines the general timing requirements for the sim interface. figure 84. sim clock timing diagram table 97. sim timing parameters, high drive strength id parameter symbol min max unit si1 sim clock frequency (simx_clky) 1 , 1 50% duty cycle clock s freq 0.01 25 mhz si2 sim clock rise time (simx_clky) 2 2 with c = 50 pf s rise ?0 . 0 9 (1/s freq )ns si3 sim clock fall time (simx_clky) 3 3 with c = 50 pf s fall ?0 . 0 9 (1/s freq )ns si4 sim input transition time (simx_datay_rx_tx, simx_simpdy) s trans 10 25 ns si5 sim i/o rise time / fall time(simx_datay_rx_tx) 4 4 with cin = 30 pf, cout = 30 pf tr/ t f ? 1 s si6 sim rst rise time / fall time(simx_rsty) 5 5 with cin = 30 pf tr/ t f ? 1 s simx_clky si2 si3 1/si1
i.mx51 applications processors for consumer and industrial products, rev. 6 128 freescale semiconductor electrical characteristics 4.7.12.1 reset sequence 4.7.12.1.1 cards with internal reset the sequence of reset for this kind of sim cards is as follows (see figure 85 ): ? after power up, the clock signal is enabled on simx_clky(time t0) ? after 200 clock cycles, rx must be high. ? the card must send a response on rx acknowl edging the reset between 400 and 40000 clock cycles after t0. figure 85. internal-reset card reset sequence 4.7.12.1.2 cards with active low reset the sequence of reset for this kind of card is as follows (see figure 86 ): ? after power-up, the clock signal is enabled on simx_clky (time t0) ? after 200 clock cycles, simx_datay_rx_tx must be high. ? simx_rsty must remain low for at least 40000 clock cycles after t0 (no response is to be received on rx during those 40000 clock cycles) ? simx_rsty is set high (time t1) ? simx_rsty must remain high for at least 40000 clock cycles after t1 and a response must be received on simx_datay_rx_tx between 400 and 40000 clock cycles after t1. simx_sveny simx_clky simx_datay_rx_tx 2 t0 1 response 2 1 < 200 clock cycles < 40000 clock cycles 400 clock cycles <
electrical characteristics i.mx51 applications processors for consumer and industrial products, rev. 6 freescale semiconductor 129 figure 86. active-low-reset cards reset sequence 4.7.12.2 power down sequence power down sequence for sim interface is as follows: ? simx_simpdy port detects the removal of the sim card ? simx_rsty goes low ? simx_clky goes low ? simx_datay_rx_tx goes low ? simx_sveny goes low simx_sveny simx_clky simx_datay_rx_tx 2 t0 1 response simx_rsty t1 1 2 < 200 clock cycles < 40000 clock cycles 400 clock cycles < 3 3 3 400000 clock cycles <
i.mx51 applications processors for consumer and industrial products, rev. 6 130 freescale semiconductor electrical characteristics each of these steps is done in one ckil period (usually 32 khz). power-down can be started because of a sim card removal detection or launched by the processor. figure 87 and table 98 shows the usual timing requirements for this sequence, with fckil = ckil frequency value. figure 87. smartcard interface power down ac timing table 98. timing requirements for power down sequence id parameter symbol min max unit si7 sim reset to sim clock stop s rst2clk 0.9 1/fckil 1.1 1/fckil ns si8 sim reset to sim tx data low s rst2dat 1.8 1/fckil 2.2 1/fckil ns si9 sim reset to sim voltage enable low s rst2ven 2.7 1/fckil 3.3 1/fckil ns si10 sim presence detect to sim reset low s pd2rst 0.9 1/fckil 1.1 1/fckil ns simx_simpdy simx_rsty simx_clky simx_datay_rx_tx simx_sveny si7 si8 si9 si10
electrical characteristics i.mx51 applications processors for consumer and industrial products, rev. 6 freescale semiconductor 131 4.7.13 scan jtag controller (sjc) timing parameters figure 88 depicts the sjc test clock input timing. figure 89 depicts the sjc boundary scan timing. figure 91 depicts the trst timing with respect to tck. figure 90 depicts the sjc test access port. signal parameters are listed in table 99 . figure 88. test clock input timing diagram figure 89. boundary scan (jtag) timing diagram tck (input) vm vm vih vil sj1 sj2 sj2 sj3 sj3 tck (input) data inputs data outputs data outputs data outputs vih vil input data valid output data valid output data valid sj4 sj5 sj6 sj7 sj6
i.mx51 applications processors for consumer and industrial products, rev. 6 132 freescale semiconductor electrical characteristics figure 90. test access port timing diagram figure 91. trst timing diagram table 99. jtag timing id parameter 1,2 all frequencies unit min max sj0 tck frequency of operation 1/(3?t dc ) 1 0.001 22 mhz sj1 tck cycle time in crystal mode 45 ? ns sj2 tck clock pulse width measured at v m 2 22.5 ? ns sj3 tck rise and fall times ? 3 ns sj4 boundary scan input data set-up time 5 ? ns sj5 boundary scan input data hold time 24 ? ns sj6 tck low to output data valid ? 40 ns sj7 tck low to output high impedance ? 40 ns sj8 tms, tdi data set-up time 5 ? ns tck (input) tdi (input) tdo (output) tdo (output) tdo (output) vih vil input data valid output data valid output data valid tms sj8 sj9 sj10 sj11 sj10 tck (input) trst (input) sj13 sj12
electrical characteristics i.mx51 applications processors for consumer and industrial products, rev. 6 freescale semiconductor 133 4.7.14 spdif timing parameters table 100 shows the timing parameters for the sony/philips digital interconnect format (spdif). 4.7.15 ssi timing parameters this section describes the timing parameters of the ss i module. the connectivity of the serial synchronous interfaces is summarized in table 101 . sj9 tms, tdi data hold time 25 ? ns sj10 tck low to tdo data valid ? 44 ns sj11 tck low to tdo high impedance ? 44 ns sj12 trst assert time 100 ? ns sj13 trst set-up time to tck low 40 ? ns 1 t dc = target frequency of sjc 2 v m = mid-point voltage table 100. spdif timing characteristics symbol all frequencies unit min max spdifout output (load = 50 pf) ?skew ? transition rising ? transition falling ?? ? ? 1.5 24.2 31.3 ns spdifout output (load = 30 pf) ?skew ? transition rising ? transition falling ?? ? ? 1.5 13.6 18.0 ns table 101. audmux port allocation port signal nomenclature type and access audmux port 1 ssi 1 internal audmux port 2 ssi 2 internal audmux port 3 aud3 external?aud3 i/o audmux port 4 aud4 external?eim or cspi1 i/o via iomux audmux port 5 aud5 external?eim or sd1 i/o via iomux table 99. jtag timing (continued) id parameter 1,2 all frequencies unit min max
i.mx51 applications processors for consumer and industrial products, rev. 6 134 freescale semiconductor electrical characteristics note ? the terms wl and bl used in the timing diagrams and tables refer to word length (wl) and bit length (bl). ? the ssi timing diagrams use gene ric signal names wherein the names used in the i.mx51 multimedia applications processor reference manual (mcimx51rm) are channel specific signal names. for example, a channel clock referenced in the iomuxc chapter as aud3_txc appears in the timing diagram as txc. 4.7.15.1 ssi transmitter timing with internal clock figure 92 depicts the ssi transmitter internal clock timing and table 102 lists the timing parameters for the ssi transmitter internal clock. . figure 92. ssi transmitter internal clock timing diagram audmux port 6 aud6 external?eim or disp2 via iomux audmux port 7 ssi 3 internal table 101. audmux port allocation (continued) port signal nomenclature type and access ss19 ss1 ss2 ss4 ss3 ss5 ss6 ss8 ss10 ss12 ss14 ss18 ss15 ss17 ss16 ss43 ss42 note: srxd input in synchronous mode only txc (output) txfs (wl) (output) txfs (bl) (output) rxd (input) txd (output)
electrical characteristics i.mx51 applications processors for consumer and industrial products, rev. 6 freescale semiconductor 135 note ? all the timings for the ssi are given for a non-inverted serial clock polarity (tsckp/rsckp = 0) and a non-inverted frame sync (tfsi/rfsi = 0). if the polarity of the clock and/or the frame sync have been inverted, all the timing remains valid by inverting the clock signal stck/srck and/or the frame sync stfs/srfs shown in the tables and in the figures. ? all timings are on audiomux pads when ssi is being used for data transfer. ? the terms wl and bl refer to word length (wl) and bit length (bl). ? ?tx? and ?rx? refer to the transmit and receive sections of the ssi. ? for internal frame sync operation using external clock, the fs timing is same as that of tx data (for example, during ac97 mode of operation). table 102. ssi transmitter timing with internal clock id parameter min max unit internal clock operation ss1 (tx/rx) ck clock period 81.4 ? ns ss2 (tx/rx) ck clock high period 36.0 ? ns ss3 (tx/rx) ck clock rise time ? 6.0 ns ss4 (tx/rx) ck clock low period 36.0 ? ns ss5 (tx/rx) ck clock fall time ? 6.0 ns ss6 (tx) ck high to fs (bl) high ? 15.0 ns ss8 (tx) ck high to fs (bl) low ? 15.0 ns ss10 (tx) ck high to fs (wl) high ? 15.0 ns ss12 (tx) ck high to fs (wl) low ? 15.0 ns ss14 (tx/rx) internal fs rise time ? 6.0 ns ss15 (tx/rx) internal fs fall time ? 6.0 ns ss16 (tx) ck high to stxd valid from high impedance ? 15.0 ns ss17 (tx) ck high to stxd high/low ? 15.0 ns ss18 (tx) ck high to stxd high impedance ? 15.0 ns ss19 stxd rise/fall time ? 6.0 ns synchronous internal clock operation ss42 srxd setup before (tx) ck falling 30 ? ns ss43 srxd hold after (tx) ck falling 0.0 ? ns ss52 loading ? 25.0 pf
i.mx51 applications processors for consumer and industrial products, rev. 6 136 freescale semiconductor electrical characteristics 4.7.15.2 ssi receiver timing with internal clock figure 93 depicts the ssi receiver internal clock timing and table 103 lists the timing parameters for the ssi receiver internal clock. figure 93. ssi receiver internal clock timing diagram table 103. ssi receiver timing with internal clock id parameter min max unit internal clock operation ss1 (tx/rx) ck clock period 81.4 ? ns ss2 (tx/rx) ck clock high period 36.0 ? ns ss3 (tx/rx) ck clock rise time ? 6.0 ns ss4 (tx/rx) ck clock low period 36.0 ? ns ss5 (tx/rx) ck clock fall time ? 6.0 ns ss7 (rx) ck high to fs (bl) high ? 15.0 ns ss9 (rx) ck high to fs (bl) low ? 15.0 ns ss11 (rx) ck high to fs (wl) high ? 15.0 ns ss13 (rx) ck high to fs (wl) low ? 15.0 ns ss20 srxd setup time before (rx) ck low 30 ? ns ss21 srxd hold time after (rx) ck low 0.0 ? ns ss50 ss48 ss1 ss4 ss2 ss51 ss20 ss21 ss49 ss7 ss9 ss11 ss13 ss47 ss3 ss5 txc (output) txfs (bl) (output) txfs (wl) (output) rxd (input) rxc (output)
electrical characteristics i.mx51 applications processors for consumer and industrial products, rev. 6 freescale semiconductor 137 note ? all the timings for the ssi are given for a non-inverted serial clock polarity (tsckp/rsckp = 0) and a non-inverted frame sync (tfsi/rfsi = 0). if the polarity of the clock and/or the frame sync have been inverted, all the timing remains valid by inverting the clock signal stck/srck and/or the frame sync stfs/srfs shown in the tables and in the figures. ? all timings are on audiomux pads when ssi is being used for data transfer. ? ?tx? and ?rx? refer to the transmit and receive sections of the ssi. ? the terms wl and bl refer to word length (wl) and bit length (bl). ? for internal frame sync operation using external clock, the fs timing is same as that of tx data (for example, during ac97 mode of operation). oversampling clock operation ss47 oversampling clock period 15.04 ? ns ss48 oversampling clock high period 6.0 ? ns ss49 oversampling clock rise time ? 3.0 ns ss50 oversampling clock low period 6.0 ? ns ss51 oversampling clock fall time ? 3.0 ns table 103. ssi receiver timing with internal clock (continued) id parameter min max unit
i.mx51 applications processors for consumer and industrial products, rev. 6 138 freescale semiconductor electrical characteristics 4.7.15.3 ssi transmitter timing with external clock figure 94 depicts the ssi transmitter external clock timing and table 104 lists the timing parameters for the ssi transmitter external clock. figure 94. ssi transmitter external clock timing diagram table 104. ssi transmitter timing with external clock id parameter min max unit external clock operation ss22 (tx/rx) ck clock period 81.4 ? ns ss23 (tx/rx) ck clock high period 36.0 ? ns ss24 (tx/rx) ck clock rise time ? 6.0 ns ss25 (tx/rx) ck clock low period 36.0 ? ns ss26 (tx/rx) ck clock fall time ? 6.0 ns ss27 (tx) ck high to fs (bl) high ?10.0 15.0 ns ss29 (tx) ck high to fs (bl) low 10.0 ? ns ss31 (tx) ck high to fs (wl) high ?10.0 15.0 ns ss33 (tx) ck high to fs (wl) low 10.0 ? ns ss37 (tx) ck high to stxd valid from high impedance ? 15.0 ns ss38 (tx) ck high to stxd high/low ? 30 ns ss45 ss33 ss24 ss26 ss25 ss23 note: srxd input in synchronous mode only ss31 ss29 ss27 ss22 ss44 ss39 ss38 ss37 ss46 txc (input) txfs (bl) (input) txfs (wl) (input) txd (output) rxd (input)
electrical characteristics i.mx51 applications processors for consumer and industrial products, rev. 6 freescale semiconductor 139 note ? all the timings for the ssi are given for a non-inverted serial clock polarity (tsckp/rsckp = 0) and a non-inverted frame sync (tfsi/rfsi = 0). if the polarity of the clock and/or the frame sync have been inverted, all the timing remains valid by inverting the clock signal stck/srck and/or the frame sync stfs/srfs shown in the tables and in the figures. ? all timings are on audiomux pads when ssi is being used for data transfer. ? ?tx? and ?rx? refer to the transmit and receive sections of the ssi. ? the terms wl and bl refer to word length (wl) and bit length (bl). ? for internal frame sync operation using external clock, the fs timing is same as that of tx data (for example, during ac97 mode of operation). ss39 (tx) ck high to stxd high impedance ? 15.0 ns synchronous external clock operation ss44 srxd setup before (tx) ck falling 10.0 ? ns ss45 srxd hold after (tx) ck falling 2.0 ? ns ss46 srxd rise/fall time ? 6.0 ns table 104. ssi transmitter timing with external clock (continued) id parameter min max unit
i.mx51 applications processors for consumer and industrial products, rev. 6 140 freescale semiconductor electrical characteristics 4.7.15.4 ssi receiver timing with external clock figure 95 depicts the ssi receiver external clock timing and table 105 lists the timing parameters for the ssi receiver external clock. figure 95. ssi receiver external clock timing diagram table 105. ssi receiver timing with external clock id parameter min max unit external clock operation ss22 (tx/rx) ck clock period 81.4 ? ns ss23 (tx/rx) ck clock high period 36 ? ns ss24 (tx/rx) ck clock rise time ? 6.0 ns ss25 (tx/rx) ck clock low period 36 ? ns ss26 (tx/rx) ck clock fall time ? 6.0 ns ss28 (rx) ck high to fs (bl) high ?10 15.0 ns ss30 (rx) ck high to fs (bl) low 10 ? ns ss32 (rx) ck high to fs (wl) high ?10 15.0 ns ss34 (rx) ck high to fs (wl) low 10 ? ns ss35 (tx/rx) external fs rise time ? 6.0 ns ss36 (tx/rx) external fs fall time ? 6.0 ns ss40 srxd setup time before (rx) ck low 10 ? ns ss41 srxd hold time after (rx) ck low 2 ? ns ss24 ss34 ss35 ss30 ss28 ss26 ss25 ss23 ss40 ss22 ss32 ss36 ss41 txc (input) txfs (bl) (input) txfs (wl) (input) rxd (input)
electrical characteristics i.mx51 applications processors for consumer and industrial products, rev. 6 freescale semiconductor 141 note ? all the timings for the ssi are given for a non-inverted serial clock polarity (tsckp/rsckp = 0) and a non-inverted frame sync (tfsi/rfsi = 0). if the polarity of the clock and/or the frame sync have been inverted, all the timing remains valid by inverting the clock signal stck/srck and/or the frame sync stfs/srfs shown in the tables and in the figures. ? all timings are on audiomux pads when ssi is being used for data transfer. ? ?tx? and ?rx? refer to the transmit and receive sections of the ssi. ? the terms wl and bl refer to word length (wl) and bit length (bl). ? for internal frame sync operation using external clock, the fs timing is same as that of tx data (for example, during ac97 mode of operation). 4.7.16 uart table 106 shows the uart i/o configuration based on which mode is enabled. 4.7.16.1 uart electrical this section describes the electrical information of the uart module. table 106. uart i/o configuration vs. mode port dte mode dce mode direction description direction description rts output rts from dte to dce input rts from dte to dce cts input cts from dce to dte output cts from dce to dte dtr output dtr from dte to dce input dtr from dte to dce dsr input dsr from dce to dte output dsr from dce to dte dcd input dcd from dce to dte output dcd from dce to dte ri input ring from dce to dte output ring from dce to dte txd_mux input serial data from dce to dte output serial data from dce to dte rxd_mux output serial data from dte to dce input serial data from dte to dce
i.mx51 applications processors for consumer and industrial products, rev. 6 142 freescale semiconductor electrical characteristics 4.7.16.1.1 uart rs-232 serial mode timing uart transmitter figure 96 depicts the transmit timing of uart in rs-232 serial mode, with 8 data bit/1 stop bit format. table 107 lists the uart rs-232 serial mode transmit timing characteristics. figure 96. uart rs-232 serial mode transmit timing diagram uart receiver figure 97 depicts the rs-232 serial mode receive timing, with 8 data bit/1 stop bit format. table 108 lists serial mode receive timing characteristics. figure 97. uart rs-232 serial mode receive timing diagram 4.7.16.1.2 uart irda mode timing the following subsections give the uart transmit and receive timings in irda mode. table 107. uart rs-232 serial mode transmit timing diagram id parameter symbol min max units ua1 transmit bit time t tbit 1/f baud_rate 1 -t ref_clk 2 1 1/f baud_rate : baud rate frequency. the maximum baud rate the uart can support is (ipg_perclk frequency)/16. 2 t ref_clk : the period of uart reference clock ref_clk (ipg_perclk after rfdiv divider). 1/f baud_rate +t ref_clk ? table 108. uart rs-232 serial mode transmit timing diagram id parameter symbol min max units ua1 receive bit time 1 1 the uart receiver can tolerate 1/(16 fbaud_rate) tolerance in each bit. but accumulation tolerance in one frame must not exceed 3/(16 fbaud_rate). t rbit 1/f baud_rate 2 -1/(16 f baud_rate ) 2 f baud_rate : baud rate frequency. the maximum baud rate the uart can support is (ipg_perclk frequency)/16. 1/f baud_rate +1/(16 f baud_rate )?
electrical characteristics i.mx51 applications processors for consumer and industrial products, rev. 6 freescale semiconductor 143 uart irda mode transmitter figure 98 depicts the uart irda mode transmit timing, with 8 data bit/1 stop bit format. table 109 lists the transmit timing characteristics. figure 98. uart irda mode transmit timing diagram uart irda mode receiver figure 99 depicts the uart irda mode receive timing, with 8 data bit/1 stop bit format. table 110 lists the receive timing characteristics. figure 99. uart irda mode receive timing diagram table 109. irda mode transmit timing parameters id parameter symbol min max units ua3 transmit bit time in irda mode t tirbit 1/f baud_rate 1 -t ref_clk 2 1 f baud_rate : baud rate frequency. the maximum baud rate the uart can support is (ipg_perclk frequency)/16. 2 tref_clk: the period of uart reference clock ref_clk (ipg_perclk after rfdiv divider). 1/f baud_rate +t ref_clk ? ua4 transmit ir pulse duration t tirpulse (3/16) ( 1 f baud_rate )-t ref_clk (3/16) ( 1 f baud_rate )+t ref_clk ? table 110. irda mode receive timing parameters id parameter symbol min max units ua5 receive bit time 1 in irda mode 1 the uart receiver can tolerate 1/(16 f baud_rate ) tolerance in each bit. but accumulation tolerance in one frame must not exceed 3/(16 f baud_rate ). t rirbit 1/f baud_rate 2 - 1/(16 f baud_rate ) 1/f baud_rate + 1/(16 f baud_rate ) ? ua6 receive ir pulse duration t rirpulse 1.41 us (5/16) (1/f baud_rate )?
i.mx51 applications processors for consumer and industrial products, rev. 6 144 freescale semiconductor electrical characteristics 4.7.17 usboh3 parameters this section describes the electrical parameters of the usb otg port and usb host ports. for on-chip usb phy parameters see section 4.7.19, ?usb phy parameters .? 4.7.17.1 usb serial interface in order to support four serial different interfaces, the usb serial transceiver can be configured to operate in one of four modes: ? dat_se0 bidirectional, 3-wire mode ? dat_se0 unidirectional, 6-wire mode ? vp_vm bidirectional, 4-wire mode ? vp_vm unidirectional, 6-wire mode the usb controller does not support ulpi serial mode . only the legacy serial mode is supported. table 111 shows the serial mode signal map for 6-pin full speed/low speed (fsls) serial mode. table 112 shows the serial mode signal map for 3-pin fsls serial mode. 2 fbaud_rate: baud rate frequency. the maximum baud rate the uart can support is (ipg_perclk frequency)/16. table 111. serial mode signal map for 6-pin fsls serial mode signal maps to direction description tx_enable data(0) in active high transmit enable tx_dat data(1) in transmit differential data on d+/d? tx_se0 data(2) in transmit single-ended zero on d+/d? int data(3) out active high interrupt indication must be asserted whenever any unmasked interrupt occurs rx_dp data(4) out single-ended receive data from d+ rx_dm data(5) out single-ended receive data from d? rx_rcv data(6) out differential receive data from d+/d? reserved data(7) out reserved the phy must drive this signal low table 112. serial mode signal map for 3-pin fsls serial mode signal maps to direction description tx_enable data(0) in active high transmit enable dat data(1) i/o transmit differential data on d+/d? when tx_enable is high receive differential data on d+/d? when tx_enable is low se0 data(2) i/o transmit single-ended zero on d+/d? when tx_enable is high receive single-ended zero on d+/d? when tx_enable is low int data(3) out active high interrupt indication must be asserted whenever any unmasked interrupt occurs
electrical characteristics i.mx51 applications processors for consumer and industrial products, rev. 6 freescale semiconductor 145 4.7.17.1.1 usb dat_se0 bi-directional mode table 113 shows the signal definitions in dat_se0 bi-directional mode and figure 100 shows the usb transmit waveform in dat_se0 bi-directional mode. figure 100. usb transmit waveform in dat_se0 bi-directional mode figure 101 shows the usb receive waveform in dat_se0 bi-directional mode and table 114 shows the definitions of usb receive waveform in dat_se0 bi-directional mode. figure 101. usb receive waveform in dat_se0 bi-directional mode table 113. signal definitions?dat_se0 bi-directional mode name direction signal description usb_txoe_b out transmit enable, active low usb_dat_vp out in tx data when usb_txoe_b is low differential rx data when usb_txoe_b is high usb_se0_vm out in se0 drive when usb_txoe_b is low se0 rx indicator when usb_txoe_b is high usb_dat_vp usb_se0_vm us1 us2 tra ns m it us4 usb_txoe_b us3 us8 us7 usb_dat_vp usb_se0_vm usb_txoe_b receive usb_se0_vm
i.mx51 applications processors for consumer and industrial products, rev. 6 146 freescale semiconductor electrical characteristics 4.7.17.1.2 usb dat_se0 unidirectional mode table 115 shows the signal definitions in dat_se0 unidirectional mode figure 102 and figure 103 shows the usb transmit/receive waveform in dat_se0 uni-directional mode respectively. figure 102. usb transmit waveform in dat_se0 uni-directional mode table 114. definitions of usb receive waveform in dat_se0 bi-directional mode id parameter signal name direction min max unit conditions/ reference signal us1 tx rise/fall time usb_dat_vp out ? 5.0 ns 50 pf us2 tx rise/fall time usb_se0_vm out ? 5.0 ns 50 pf us3 tx rise/fall time usb_txoe_b out ? 5.0 ns 50 pf us4 tx duty cycle usb_dat_vp out 49.0 51.0 % ? us7 rx rise/fall time usb_dat_vp in ? 3.0 ns 35 pf us8 rx rise/fall time usb_se0_vm in ? 3.0 ns 35 pf table 115. signal definitions?dat_se0 unidirectional mode name direction signal description usb_txoe_b out transmit enable, active low usb_dat_vp out tx data when usb_txoe_b is low usb_se0_vm out se0 drive when usb_txoe_b is low usb_vp1 in buffered data on dp when usb_txoe_b is high usb_vm1 in buffered data on dm when usb_txoe_b is high usb_rcv in differential rx data when usb_txoe_b is high usb_dat_vp usb_se0_vm us9 us10 tr a n s m i t us12 usb_txoe_b us11
electrical characteristics i.mx51 applications processors for consumer and industrial products, rev. 6 freescale semiconductor 147 figure 103. usb receive waveform in dat_se0 uni-directional mode table 116 shows the usb port timing specification in dat_se0 uni-directional mode. 4.7.17.1.3 usb vp_vm bi-directional mode table 117 shows the signal definitions in vp_vm bi-directional mode. figure 104 and figure 105 shows the usb transmit/receive waveform in vp_vm bi-directional mode respectively. table 116. usb port timing specification in dat_se0 uni-directional mode id parameter signal name signal source min max unit condition/ reference signal us9 tx rise/fall time usb_dat_vp out ? 5.0 ns 50 pf us10 tx rise/fall time usb_se0_vm out ? 5.0 ns 50 pf us11 tx rise/fall time usb_txoe_b out ? 5.0 ns 50 pf us12 tx duty cycle usb_dat_vp out 49.0 51.0 % ? us15 rx rise/fall time usb_vp1 in ? 3.0 ns 35 pf us16 rx rise/fall time usb_vm1 in ? 3.0 ns 35 pf us17 rx rise/fall time usb_rcv in ? 3.0 ns 35 pf table 117. signal definitions?vp_vm bi-directional mode name direction signal description usb_txoe_b out transmit enable, active low usb_dat_vp out (tx) in (rx) tx vp data when usb_txoe_b is low rx vp data when usb_txoe_b is high usb_se0_vm out (tx) in (rx) tx vm data when usb_txoe_b low rx vm data when usb_txoe_b high usb_rcv in differential rx data us16 us15/us17 usb_dat_vp usb_txoe_b receive usb_se0_vm usb_rcv
i.mx51 applications processors for consumer and industrial products, rev. 6 148 freescale semiconductor electrical characteristics figure 104. usb transmit waveform in vp_vm bi-directional mode figure 105. usb receive waveform in vp_vm bi-directional mode table 118 shows the usb port timing specification in vp_vm bi-directional mode. table 118. usb port timing specification in vp_vm bi-directional mode id parameter signal name direction min max unit condition/reference signal us18 tx rise/fall time usb_dat_vp out ? 5.0 ns 50 pf us19 tx rise/fall time usb_se0_vm out ? 5.0 ns 50 pf us20 tx rise/fall time usb_txoe_b out ? 5.0 ns 50 pf us21 tx duty cycle usb_dat_vp out 49.0 51.0 % ? us22 tx overlap usb_se0_vm out ?3.0 3.0 ns usb_dat_vp usb_dat_vp usb_se0_vm us18 us19 transmit usb_txoe_b us20 us22 us21 us22 usb_dat_vp usb_se0_vm us26 us28 us27 us29 usb_rcv receive
electrical characteristics i.mx51 applications processors for consumer and industrial products, rev. 6 freescale semiconductor 149 4.7.17.1.4 usb vp_vm uni-directional mode table 119 shows the signal definitions in vp_vm uni-directional mode. figure 106 and figure 107 shows the usb transmit/receive waveform in vp_vm uni-directional mode respectively. figure 106. usb transmit waveform in vp_vm unidirectional mode us26 rx rise/fall time usb_dat_vp in ? 3.0 ns 35 pf us27 rx rise/fall time usb_se0_vm in ? 3.0 ns 35 pf us28 rx skew usb_dat_vp in ?4.0 4.0 ns usb_se0_vm us29 rx skew usb_rcv in ?6.0 2.0 ns usb_dat_vp table 119. usb signal definitions?vp_vm uni-directional mode name direction signal description usb_txoe_b out transmit enable, active low usb_dat_vp out tx vp data when usb_txoe_b is low usb_se0_vm out tx vm data when usb_txoe_b is low usb_vp1 in rx vp data when usb_txoe_b is high usb_vm1 in rx vm data when usb_txoe_b is high usb_rcv in differential rx data table 118. usb port timing specification in vp_vm bi-directional mode (continued) id parameter signal name direction min max unit condition/reference signal usb_dat_vp usb_se0_vm us30 us31 transmit usb_txoe_b us32 us34 us33 us34
i.mx51 applications processors for consumer and industrial products, rev. 6 150 freescale semiconductor electrical characteristics figure 107. usb receive waveform in vp_vm uni-directional mode table 120 shows the usb port timing specification in vp_vm uni-directional mode. table 120. usb timing specification in vp_vm unidirectional mode id parameter signal direction min max unit conditions / reference signal us30 tx rise/fall time usb_dat_vp out ? 5.0 ns 50 pf us31 tx rise/fall time usb_se0_vm out ? 5.0 ns 50 pf us32 tx rise/fall time usb_txoe_b out ? 5.0 ns 50 pf us33 tx duty cycle usb_dat_vp out 49.0 51.0 % ? us34 tx overlap usb_se0_vm out ?3.0 3.0 ns usb_dat_vp us38 rx rise/fall time usb_vp1 in ? 3.0 ns 35 pf us39 rx rise/fall time usb_vm1 in ? 3.0 ns 35 pf us40 rx skew usb_vp1 in ?4.0 4.0 ns usb_vm1 us41 rx skew usb_rcv in ?6.0 2.0 ns usb_vp1 us38 usb_vm1 receive usb_rcv usb_txoe_b us41 us40 us39 usb_vp1
electrical characteristics i.mx51 applications processors for consumer and industrial products, rev. 6 freescale semiconductor 151 4.7.18 usb parallel interface timing electrical and timing specifications of parallel inte rface are presented in the subsequent sections. table 121 shows the signal definitions in parallel mode. figure 108 shows the usb transmit/receive waveform in parallel mode. table 122 shows the usb timing specification for ulpi parallel mode. figure 108. usb transmit/receive waveform in parallel mode table 121. signal definitions?parallel interface (normal ulpi) name direction signal description usb_clk in interface clock. all interface signals are synchronous to clock. usb_data[7:0] i/o bi-directional data bus, driven low by the link during idle. bus ownership is determined by dir. usb_dir in direction. control the direction of the data bus. usb_stp out stop. the link asserts this signal for 1 clock cycle to stop the data stream currently on the bus. usb_nxt in next. the phy asserts this signal to throttle the data. table 122. usb timing specification for ulpi parallel mode id parameter min max unit conditions/ reference signal us15 setup time (dir, nxt in, data in) 6 ? ns 10 pf us16 hold time (dir, nxt in, data in) 0 ? ns 10 pf us17 output delay time (stp out, data out) for h3 routed to disp2 i/o 1 and h1 1 h3 routed to nandf i/o is recommended for full and low-speed use only. ? 9 ns 10 pf us17 output delay time (stp out, data out) for h2 ? 11 ns 10 pf usb_stp usb_dir/nxt us17 us16 usb_data us15 us16 us15 us17 usb_clk
i.mx51 applications processors for consumer and industrial products, rev. 6 152 freescale semiconductor electrical characteristics 4.7.19 usb phy parameters this section describes the usb phy parameters. 4.7.19.1 usb phy ac parameters table 123 lists the ac timing parameters for usb phy. 4.7.19.2 usb phy additional electrical parameters table 124 lists the parameters for additional electrical characteristics for usb phy. 4.7.19.3 usb phy system clocking (sysclk) table 125 lists the usb phy system clocking parameters. table 123. usb phy ac timing parameters parameter conditions min typ max unit trise 1.5 mbps 12 mbps 480 mbps 75 4 0.5 ? 300 20 ns tfall 1.5 mbps 12 mbps 480 mbps 75 4 0.5 ? 300 20 ns jitter 1.5 mbps 12 mbps 480 mbps ??1 0 1 0.2 ns table 124. additional electrical characteristics for usb phy parameter conditions min typ max unit vcm dc (dc level measured at receiver connector) hs mode ls/fs mode ?0.05 0.8 ?0.5 2.5 v crossover voltage ls mode fs mode 1.3 1.3 ?2 2 v power supply ripple noise (analog 3.3 v) <160 mhz ?50 0 50 mv power supply ripple noise (analog 2.5 v) <1.2 mhz >1.2 mhz ?10 ?50 0 0 10 50 mv power supply ripple noise (digital 1.2) all conditions ?50 0 50 mv table 125. usb phy system clocking parameters parameter conditions min typ max unit clock deviation ? ?150 ? 150 ppm rise/fall time ? ? ? 200 ps
package information and contact assignments i.mx51 applications processors for consumer and industrial products, rev. 6 freescale semiconductor 153 4.7.19.4 usb phy voltage thresholds table 126 lists the usb phy voltage thresholds. 5 package information and contact assignments this section includes the contact assignment information and mechanical package drawing. 5.1 13 x 13 mm package information this section contains the outline drawing, signal assi gnment map, ground/power/reference id (by ball grid location) for the 13 13 mm, 0.5 mm pitch package. jitter (peak-peak) <1.2 mhz 0 ? 50 ps jitter (peak-peak) >1.2 mhz 0 ? 100 ps duty-cycle ? 40 ? 60 % table 126. vbus comparators thresholds parameter conditions min typ max unit a-device session valid ? 0.8 1.4 2.0 v b-device session valid ? 0.8 1.4 4.0 v b-device session end ? 0.2 0.45 0.8 v vbus valid comparator threshold 1 1 for vbus maximum rating, see ta b l e 1 1 on page 18 ?4 . 44 . 64 . 7 5v table 125. usb phy system clocking parameters (continued) parameter conditions min typ max unit
i.mx51 applications processors for consumer and industrial products, rev. 6 154 freescale semiconductor package information and contact assignments 5.1.1 bga?case 2058 13 x 13 mm, 0.5 mm pitch figure 109 shows the top view, bottom view, and side view of the 13 13 mm package. figure 109. package: case 2058?0.5 mm pitch 5.1.1.1 13 x 13 mm package drawing notes the following notes apply to figure 109 . 1 all dimensions in millimeters. 2 dimensioning and tolerancing per asme y14.5m-1994. 3 maximum solder ball diameter measured parallel to datum a.
package information and contact assignments i.mx51 applications processors for consumer and industrial products, rev. 6 freescale semiconductor 155 4 datum a, the seating plane, is determined by the spherical crowns of the solder balls. 5 parallelism measurement shall exclude any effect of mark on top surface of package. 5.1.2 13 x 13 mm, 0.5 pitch ball assignment lists table 127 shows the device connection list for ground, power, sense, and reference contact signals alpha-sorted by name. table 128 displays an alpha-sorted list of the signal assignments. table 129 provides a listing of the no-connect contacts. 5.1.2.1 13 x 13 mm ball contact assignments table 127 shows the device connection list for ground, power, sense, and reference contact signals alpha-sorted by name. table 127. 13 x 13 mm ground, power, sense, and reference contact assignments contact name contact assignment ahvddrgb v15, v16 ahvssrgb v13, v14 gnd a1, a24, a25, b1, b25, e7, e13, e16, e19, g5, j13, j14, k5, k13, k14, k15, l13, l14, l15, l21, m12, m13, m14, m15, n5, n6, n8, n9, n10, n11, p8, p9, p11, p21, r8, r9, r10, r11, r12, t8, t9, t10, t11, t12, t13, u5, u9, u10, u11, u12, u13, u21, w5, aa7, aa10, aa13, aa16, aa19, ad1, ad2, ad25, ae1, ae24, ae25 gnd_ana_pll_a ae3 gnd_ana_pll_b ac25 gnd_dig_pll_a ae2 gnd_dig_pll_b ad24 ngnd_osc ac23 ngnd_tv_back ab22 ngnd_usbphy l23 nvcc_emi u8, v8 nvcc_emi_dram l5, m5, r5, t5, y5, aa5 nvcc_hs10 m20 nvcc_hs4_1 l20 nvcc_hs4_2 p20 nvcc_hs6 n20 nvcc_i2c v11 nvcc_ipu2 v20 nvcc_ipu4 n16 nvcc_ipu5 k16 nvcc_ipu6 m16
i.mx51 applications processors for consumer and industrial products, rev. 6 156 freescale semiconductor package information and contact assignments nvcc_ipu7 h22 nvcc_ipu8 v22 nvcc_ipu9 l16 nvcc_nandf_a j8 nvcc_nandf_b h8 nvcc_nandf_c h9 nvcc_osc ad22 nvcc_per10 h12 nvcc_per11 h11 nvcc_per12 h15 nvcc_per13 h14 nvcc_per14 v9 nvcc_per15 h16 nvcc_per17 j16 nvcc_per3 v10 nvcc_per5 d20 nvcc_per8 j15 nvcc_per9 h10 nvcc_srtc_pow v12 nvcc_tv_back ac22 nvcc_usbphy p16 rrefext k18 sgnd p10 svcc n13 svddgp m11 tvdac_dhvdd ab21 vbus l22 vcc n12, n14, n15, p12, p13, p14, p15, r13, r14, r15, t14, t15, t16, u14, u15, u16 vdd_ana_pll_a ad4 vdd_ana_pll_b ac24 vdd_dig_pll_a ad3 vdd_dig_pll_b ab23 vdd_fuse p6 table 127. 13 x 13 mm ground, power, sense, and reference contact assignments (continued) contact name contact assignment
package information and contact assignments i.mx51 applications processors for consumer and industrial products, rev. 6 freescale semiconductor 157 5.1.2.2 13 x 13 mm signal assignments, power rails, and i/o table 128 shows signal assignment connect list including the associated power supplies. table 132 lists the contacts that can be overridden with fuse settings. vdda h13, n18, r6, t6, y16 vdda33 r16 vddgp e10, j9, j10, j11, j12, k8, k9, k10, k11, k12, l6, l8, l9, l10, l11, l12, m6, m8, m9, m10 vref u6 vrefout ab20 vreg l24 table 128. 13 x 13 mm signal assignments, power rails, and i/o contact name contact assignment power rail i/o buffer type direction after reset 1 configuraton after reset 1 aud3_bb_ck c9 nvcc_per9 gpio input keeper aud3_bb_fs c8 nvcc_per9 gpio input keeper aud3_bb_rxd b8 nvcc_per9 gpio input keeper aud3_bb_txd b7 nvcc_per9 gpio input keeper boot_mode0 w22 nvcc_per3 lvio input 100 k pull-up boot_mode1 aa24 nvcc_per3 lvio input 100 k pull-up ckih1 ab24 nvcc_per3 analog input analog ckih2 aa23 nvcc_per3 analog input analog ckil aa22 nvcc_srtc_pow gpio input standard cmos clk_ss y22 nvcc_per3 lvio input 100 k pull-up comp 2 ac20 ahvddrgb analog input analog csi1_d10 r24 nvcc_hs10 hsgpio input keeper csi1_d11 r25 nvcc_hs10 hsgpio input keeper csi1_d12 p22 nvcc_hs10 hsgpio input keeper csi1_d13 p23 nvcc_hs10 hsgpio input keeper csi1_d14 p24 nvcc_hs10 hsgpio input keeper csi1_d15 p25 nvcc_hs10 hsgpio input keeper csi1_d16 n24 nvcc_hs10 hsgpio input keeper csi1_d17 n25 nvcc_hs10 hsgpio input keeper csi1_d18 n23 nvcc_hs10 hsgpio input keeper table 127. 13 x 13 mm ground, power, sense, and reference contact assignments (continued) contact name contact assignment
i.mx51 applications processors for consumer and industrial products, rev. 6 158 freescale semiconductor package information and contact assignments csi1_d19 n22 nvcc_hs10 hsgpio input keeper csi1_d8 a20 nvcc_per8 gpio input keeper csi1_d9 b20 nvcc_per8 gpio input keeper csi1_hsync c19 nvcc_per8 gpio input keeper csi1_mclk f19 nvcc_per8 gpio input keeper csi1_pixclk d19 nvcc_per8 gpio input keeper csi1_vsync b19 nvcc_per8 gpio input keeper csi2_d12 f11 nvcc_per9 gpio input keeper csi2_d13 d8 nvcc_per9 gpio input keeper csi2_d14 m25 nvcc_hs4_1 hsgpio input keeper csi2_d15 m24 nvcc_hs4_1 hsgpio input keeper csi2_d16 m23 nvcc_hs4_1 hsgpio input keeper csi2_d17 m22 nvcc_hs4_1 hsgpio input keeper csi2_d18 a7 nvcc_per9 gpio input keeper csi2_d19 c7 nvcc_per9 gpio input keeper csi2_hsync j20 nvcc_per8 gpio input keeper csi2_pixclk d21 nvcc_per8 gpio input keeper csi2_vsync c20 nvcc_per8 gpio input keeper cspi1_miso f12 nvcc_per10 gpio input 100 k pull-up cspi1_mosi d9 nvcc_per10 gpio input 100 k pull-up cspi1_rdy a8 nvcc_per10 gpio input keeper cspi1_sclk d11 nvcc_per10 gpio input 100 k pull-up cspi1_ss0 d10 nvcc_per10 gpio input 100 k pull-up cspi1_ss1 f13 nvcc_per10 gpio input 100 k pull-up di_gp1 f20 nvcc_ipu6 gpio input keeper di_gp2 k20 nvcc_ipu6 gpio input keeper di_gp3 h23 nvcc_ipu7 gpio input 100 k pull-up di_gp4 k23 nvcc_ipu7 gpio input 100 k pull-up di1_d0_cs w20 nvcc_ipu2 gpio output high di1_d1_cs t18 nvcc_ipu2 gpio output high di1_disp_clk j22 nvcc_ipu6 gpio output low di1_pin11 v18 nvcc_ipu2 gpio output high table 128. 13 x 13 mm signal assignments, power rails, and i/o (continued) contact name contact assignment power rail i/o buffer type direction after reset 1 configuraton after reset 1
package information and contact assignments i.mx51 applications processors for consumer and industrial products, rev. 6 freescale semiconductor 159 di1_pin12 w25 nvcc_ipu2 gpio output high di1_pin13 w24 nvcc_ipu2 gpio output high di1_pin15 g20 nvcc_ipu6 gpio output high di1_pin2 j18 nvcc_ipu6 gpio output high di1_pin3 h20 nvcc_ipu6 gpio output high di2_disp_clk j24 nvcc_ipu7 gpio output high di2_pin2 h24 nvcc_ipu7 gpio output high di2_pin3 j25 nvcc_ipu7 gpio output high di2_pin4 j23 nvcc_ipu7 gpio input keeper disp1_dat0 t23 nvcc_hs6 hsgpio input keeper disp1_dat1 t22 nvcc_hs6 hsgpio input keeper disp1_dat10 3 e24 nvcc_ipu4 gpio input keeper disp1_dat11 1 e25 nvcc_ipu4 gpio input keeper disp1_dat12 1 e22 nvcc_ipu4 gpio input keeper disp1_dat13 1 e23 nvcc_ipu4 gpio input keeper disp1_dat14 1 d22 nvcc_ipu4 gpio input keeper disp1_dat15 1 f22 nvcc_ipu4 gpio input keeper disp1_dat16 1 f23 nvcc_ipu5 gpio input keeper disp1_dat17 1 f24 nvcc_ipu5 gpio input keeper disp1_dat18 1 g23 nvcc_ipu5 gpio input keeper disp1_dat19 1 g22 nvcc_ipu5 gpio input keeper disp1_dat2 t24 nvcc_hs6 hsgpio input keeper disp1_dat20 1 g25 nvcc_ipu5 gpio input keeper disp1_dat21 1 f25 nvcc_ipu5 gpio input keeper disp1_dat22 1 g24 nvcc_ipu5 gpio input keeper disp1_dat23 1 h25 nvcc_ipu5 gpio input keeper disp1_dat3 t25 nvcc_hs6 hsgpio input keeper disp1_dat4 r23 nvcc_hs6 hsgpio input keeper disp1_dat5 r22 nvcc_hs6 hsgpio input keeper disp1_dat6 1 d25 nvcc_ipu4 gpio input keeper disp1_dat7 1 d24 nvcc_ipu4 gpio input keeper disp1_dat8 1 c23 nvcc_ipu4 gpio input keeper table 128. 13 x 13 mm signal assignments, power rails, and i/o (continued) contact name contact assignment power rail i/o buffer type direction after reset 1 configuraton after reset 1
i.mx51 applications processors for consumer and industrial products, rev. 6 160 freescale semiconductor package information and contact assignments disp1_dat9 1 d23 nvcc_ipu4 gpio input keeper disp2_dat0 t20 nvcc_ipu8 gpio input keeper disp2_dat1 p18 nvcc_ipu8 gpio input keeper disp2_dat10 r18 nvcc_ipu9 gpio input keeper disp2_dat11 v24 nvcc_ipu9 gpio input keeper disp2_dat12 m18 nvcc_ipu9 gpio input keeper disp2_dat13 u18 nvcc_ipu9 gpio input keeper disp2_dat14 u20 nvcc_ipu9 gpio input keeper disp2_dat15 v23 nvcc_ipu9 gpio input keeper disp2_dat2 u22 nvcc_hs4_2 hsgpio input keeper disp2_dat3 u23 nvcc_hs4_2 hsgpio input keeper disp2_dat4 u24 nvcc_hs4_2 hsgpio input keeper disp2_dat5 u25 nvcc_hs4_2 hsgpio input keeper disp2_dat6 r20 nvcc_ipu8 gpio input keeper disp2_dat7 v25 nvcc_ipu8 gpio input keeper disp2_dat8 l18 nvcc_ipu9 gpio input keeper disp2_dat9 v17 nvcc_ipu9 gpio input keeper dispb2_ser_clk y25 nvcc_ipu2 gpio output high dispb2_ser_din y23 nvcc_ipu2 gpio input 100 k pull-up dispb2_ser_dio y20 nvcc_ipu2 gpio input 100 k pull-up dispb2_ser_rs w23 nvcc_ipu2 gpio output high dn k25 vdda33 analog output ? dp k24 vdda33 analog output ? dram_a0 v4 nvcc_emi_dram ddr2 output high dram_a1 v3 nvcc_emi_dram ddr2 output high dram_a10 t4 nvcc_emi_dram ddr2 output high dram_a11 r1 nvcc_emi_dram ddr2 output high dram_a12 p2 nvcc_emi_dram ddr2 output high dram_a13 r4 nvcc_emi_dram ddr2 output high dram_a14 r2 nvcc_emi_dram ddr2 output high dram_a2 u4 nvcc_emi_dram ddr2 output high dram_a3 u3 nvcc_emi_dram ddr2 output high table 128. 13 x 13 mm signal assignments, power rails, and i/o (continued) contact name contact assignment power rail i/o buffer type direction after reset 1 configuraton after reset 1
package information and contact assignments i.mx51 applications processors for consumer and industrial products, rev. 6 freescale semiconductor 161 dram_a4 u1 nvcc_emi_dram ddr2 output high dram_a5 u2 nvcc_emi_dram ddr2 output high dram_a6 t1 nvcc_emi_dram ddr2 output high dram_a7 t2 nvcc_emi_dram ddr2 output high dram_a8 t3 nvcc_emi_dram ddr2 output high dram_a9 p1 nvcc_emi_dram ddr2 output high dram_cas n4 nvcc_emi_dram ddr2 output high dram_cs0 p3 nvcc_emi_dram ddr2 output high dram_cs1 r3 nvcc_emi_dram ddr2 output high dram_d0 ac4 nvcc_emi_dram ddr2 output high dram_d1 ac3 nvcc_emi_dram ddr2 output high dram_d10 aa2 nvcc_emi_dram ddr2 output high dram_d11 aa1 nvcc_emi_dram ddr2 output high dram_d12 ab2 nvcc_emi_dram ddr2 output high dram_d13 ab1 nvcc_emi_dram ddr2 output high dram_d14 ac2 nvcc_emi_dram ddr2 output high dram_d15 ac1 nvcc_emi_dram ddr2 output high dram_d16 f2 nvcc_emi_dram ddr2 output high dram_d17 f3 nvcc_emi_dram ddr2 output high dram_d18 g3 nvcc_emi_dram ddr2 output high dram_d19 f4 nvcc_emi_dram ddr2 output high dram_d2 ab3 nvcc_emi_dram ddr2 output high dram_d20 h3 nvcc_emi_dram ddr2 output high dram_d21 g4 nvcc_emi_dram ddr2 output high dram_d22 j3 nvcc_emi_dram ddr2 output high dram_d23 h4 nvcc_emi_dram ddr2 output high dram_d24 j4 nvcc_emi_dram ddr2 output high dram_d25 j1 nvcc_emi_dram ddr2 output high dram_d26 j2 nvcc_emi_dram ddr2 output high dram_d27 h1 nvcc_emi_dram ddr2 output high dram_d28 h2 nvcc_emi_dram ddr2 output high dram_d29 g1 nvcc_emi_dram ddr2 output high table 128. 13 x 13 mm signal assignments, power rails, and i/o (continued) contact name contact assignment power rail i/o buffer type direction after reset 1 configuraton after reset 1
i.mx51 applications processors for consumer and industrial products, rev. 6 162 freescale semiconductor package information and contact assignments dram_d3 ab4 nvcc_emi_dram ddr2 output high dram_d30 g2 nvcc_emi_dram ddr2 output high dram_d31 f1 nvcc_emi_dram ddr2 output high dram_d4 aa3 nvcc_emi_dram ddr2 output high dram_d5 aa4 nvcc_emi_dram ddr2 output high dram_d6 y3 nvcc_emi_dram ddr2 output high dram_d7 y4 nvcc_emi_dram ddr2 output high dram_d8 y1 nvcc_emi_dram ddr2 output high dram_d9 y2 nvcc_emi_dram ddr2 output high dram_dqm0 v1 nvcc_emi_dram ddr2 output high dram_dqm1 v2 nvcc_emi_dram ddr2 output high dram_dqm2 m4 nvcc_emi_dram ddr2 output high dram_dqm3 n2 nvcc_emi_dram ddr2 output high dram_ras n3 nvcc_emi_dram ddr2 output high dram_sdcke0 n1 nvcc_emi_dram ddr2 output high dram_sdcke1 l1 nvcc_emi_dram ddr2 output high dram_sdclk m1 nvcc_emi_dram ddr2clk output high dram_sdclk_b m2 nvcc_emi_dram ddr2clk output high dram_sdqs0 w3 nvcc_emi_dram ddr2clk output high dram_sdqs0_b w4 nvcc_emi_dram ddr2clk output high dram_sdqs1 w2 nvcc_emi_dram ddr2clk output high dram_sdqs1_b w1 nvcc_emi_dram ddr2clk output high dram_sdqs2 k3 nvcc_emi_dram ddr2clk output high dram_sdqs2_b k4 nvcc_emi_dram ddr2clk output high dram_sdqs3 k2 nvcc_emi_dram ddr2clk output high dram_sdqs3_b k1 nvcc_emi_dram ddr2clk output high dram_sdwe m3 nvcc_emi_dram ddr2 output high eim_a16 1 y12 nvcc_emi gpio input 100 k pull-up eim_a17 1 ae6 nvcc_emi gpio input 100 k pull-up eim_a18 1 y13 nvcc_emi gpio input 100 k pull-up eim_a19 1 ae7 nvcc_emi gpio input 100 k pull-up eim_a20 1 y6 nvcc_emi gpio input 100 k pull-up table 128. 13 x 13 mm signal assignments, power rails, and i/o (continued) contact name contact assignment power rail i/o buffer type direction after reset 1 configuraton after reset 1
package information and contact assignments i.mx51 applications processors for consumer and industrial products, rev. 6 freescale semiconductor 163 eim_a21 1 ad6 nvcc_emi gpio input 100 k pull-up eim_a22 ab9 nvcc_emi gpio output high eim_a23 1 ae5 nvcc_emi gpio input 100 k pull-up eim_a24 y9 nvcc_emi gpio input 100 k pull-up eim_a25 ad5 nvcc_emi gpio input 100 k pull-up eim_a26 ab7 nvcc_emi gpio input 100 k pull-up eim_a27 ac6 nvcc_emi gpio input keeper eim_bclk y10 nvcc_emi gpio input keeper eim_cre v6 nvcc_emi gpio output high eim_cs0 y17 nvcc_emi gpio output high eim_cs1 w6 nvcc_emi gpio output high eim_cs2 ae4 nvcc_emi gpio input keeper eim_cs3 y8 nvcc_emi gpio input keeper eim_cs4 ac7 nvcc_emi gpio input keeper eim_cs5 y7 nvcc_emi gpio input keeper eim_d16 ab12 nvcc_emi gpio input keeper eim_d17 ae8 nvcc_emi gpio input keeper eim_d18 ad9 nvcc_emi gpio input keeper eim_d19 ac10 nvcc_emi gpio input keeper eim_d20 ad10 nvcc_emi gpio input keeper eim_d21 ae10 nvcc_emi gpio input keeper eim_d22 ae11 nvcc_emi gpio input keeper eim_d23 ab11 nvcc_emi gpio input keeper eim_d24 ae9 nvcc_emi gpio input keeper eim_d25 ac9 nvcc_emi gpio input keeper eim_d26 ad8 nvcc_emi gpio input keeper eim_d27 ab10 nvcc_emi gpio input keeper eim_d28 y11 nvcc_emi gpio input keeper eim_d29 ad7 nvcc_emi gpio input keeper eim_d30 ac8 nvcc_emi gpio input keeper eim_d31 ab8 nvcc_emi gpio input keeper eim_da0 ae15 nvcc_emi gpio input keeper table 128. 13 x 13 mm signal assignments, power rails, and i/o (continued) contact name contact assignment power rail i/o buffer type direction after reset 1 configuraton after reset 1
i.mx51 applications processors for consumer and industrial products, rev. 6 164 freescale semiconductor package information and contact assignments eim_da1 ad15 nvcc_emi gpio input keeper eim_da10 ac13 nvcc_emi gpio input keeper eim_da11 ae12 nvcc_emi gpio input keeper eim_da12 ae13 nvcc_emi gpio input keeper eim_da13 ad12 nvcc_emi gpio input keeper eim_da14 ac12 nvcc_emi gpio input keeper eim_da15 ad11 nvcc_emi gpio input keeper eim_da2 ac15 nvcc_emi gpio input keeper eim_da3 ab16 nvcc_emi gpio input keeper eim_da4 ae16 nvcc_emi gpio input keeper eim_da5 y18 nvcc_emi gpio input keeper eim_da6 ab15 nvcc_emi gpio input keeper eim_da7 ac14 nvcc_emi gpio input keeper eim_da8 ab14 nvcc_emi gpio input keeper eim_da9 ad13 nvcc_emi gpio input keeper eim_dtack ac5 nvcc_emi gpio input 100 k pull-up eim_eb0 ad14 nvcc_emi gpio output high eim_eb1 ae14 nvcc_emi gpio output high eim_eb2 ab13 nvcc_emi gpio input keeper eim_eb3 ac11 nvcc_emi gpio input keeper eim_lba ab5 nvcc_emi gpio output high eim_oe y14 nvcc_emi gpio output high eim_rw y15 nvcc_emi gpio output high eim_sdba0 p4 nvcc_emi_dram ddr2 output high eim_sdba1 l4 nvcc_emi_dram ddr2 output high eim_sdba2 k6 nvcc_emi_dram ddr2 output high eim_sdodt0 l2 nvcc_emi_dram ddr2 output high eim_sdodt1 l3 nvcc_emi_dram ddr2 output high eim_wait ab6 nvcc_emi gpio input 100 k pull-up extal 2 ad23 nvcc_osc analog input ? fastr_ana 2 ae22 nvcc_per3 ? input ? fastr_dig 2 ac21 nvcc_per3 ? input ? table 128. 13 x 13 mm signal assignments, power rails, and i/o (continued) contact name contact assignment power rail i/o buffer type direction after reset 1 configuraton after reset 1
package information and contact assignments i.mx51 applications processors for consumer and industrial products, rev. 6 freescale semiconductor 165 gpanaio 2 k22 nvcc_usbphy analog output ? gpio_nand c3 nvcc_nandf_a uhvio input 100 k pull-up gpio1_0 h18 nvcc_per5 gpio input keeper gpio1_1 c21 nvcc_per5 gpio input keeper gpio1_2 b23 nvcc_per5 gpio input keeper gpio1_3 a22 nvcc_per5 gpio input keeper gpio1_4 b22 nvcc_per5 gpio input keeper gpio1_5 c22 nvcc_per5 gpio input keeper gpio1_6 b24 nvcc_per5 gpio input keeper gpio1_7 a23 nvcc_per5 gpio input keeper gpio1_8 c24 nvcc_per5 gpio input keeper gpio1_9 c25 nvcc_per5 gpio input keeper i2c1_clk ab19 nvcc_i2c i2cio input 47 k pull-up i2c1_dat y19 nvcc_i2c i2cio input 47 k pull-up id l25 nvcc_usbphy analog input pull-up iob 2 ae21 ahvddrgb analog output ? iob_back 2 ad21 ? analog output ? iog 2 ae20 ahvddrgb analog output ? iog_back 2 ad20 ? analog output ? ior 2 ae19 ahvddrgb analog output ? ior_back 2 ad19 ? analog output ? jtag_de_b ac16 nvcc_per14 gpio input/ open-drain output 47 k pull-up jtag_mod ad16 nvcc_per14 gpio input 100 k pull-up jtag_tck ad18 nvcc_per14 gpio input 100 k pull-down jtag_tdi ab17 nvcc_per14 gpio input 47 k pull-up jtag_tdo ad17 nvcc_per14 gpio 3-state output keeper jtag_tms ac17 nvcc_per14 gpio input 47 k pull-up jtag_trstb ae17 nvcc_per14 gpio input 47 k pull-up key_col0 b16 nvcc_per13 gpio input 100 k pull-up key_col1 c16 nvcc_per13 gpio input 100 k pull-up table 128. 13 x 13 mm signal assignments, power rails, and i/o (continued) contact name contact assignment power rail i/o buffer type direction after reset 1 configuraton after reset 1
i.mx51 applications processors for consumer and industrial products, rev. 6 166 freescale semiconductor package information and contact assignments key_col2 d16 nvcc_per13 gpio input 100 k pull-up key_col3 4 a16 nvcc_per13 gpio output high key_col4 4 b17 nvcc_per13 gpio output low key_col5 4 a17 nvcc_per13 gpio output low key_row0 b15 nvcc_per13 gpio input 100 k pull-up key_row1 c15 nvcc_per13 gpio input 100 k pull-up key_row2 f15 nvcc_per13 gpio input 100 k pull-up key_row3 d15 nvcc_per13 gpio input 100 k pull-up nandf_ale e1 nvcc_nandf_a uhvio output high nandf_cle e2 nvcc_nandf_a uhvio output high nandf_cs0 d4 nvcc_nandf_a uhvio output high nandf_cs1 d1 nvcc_nandf_a uhvio output high nandf_cs2 d5 nvcc_nandf_a uhvio output high nandf_cs3 b2 nvcc_nandf_a uhvio output high nandf_cs4 b3 nvcc_nandf_a uhvio output low nandf_cs5 c4 nvcc_nandf_a uhvio output low nandf_cs6 a2 nvcc_nandf_b uhvio output low nandf_cs7 f7 nvcc_nandf_b uhvio output low nandf_d0 d7 nvcc_nandf_c uhvio input keeper nandf_d1 f9 nvcc_nandf_c uhvio input keeper nandf_d10 c5 nvcc_nandf_b uhvio input keeper nandf_d11 b4 nvcc_nandf_b uhvio input keeper nandf_d12 a3 nvcc_nandf_b uhvio input keeper nandf_d13 f10 nvcc_nandf_b uhvio input keeper nandf_d14 e4 nvcc_nandf_b uhvio input keeper nandf_d15 j6 nvcc_nandf_b uhvio input keeper nandf_d2 c6 nvcc_nandf_c uhvio input keeper nandf_d3 b5 nvcc_nandf_c uhvio input keeper nandf_d4 b6 nvcc_nandf_c uhvio input keeper nandf_d5 f8 nvcc_nandf_c uhvio input keeper nandf_d6 a6 nvcc_nandf_c uhvio input keeper nandf_d7 a5 nvcc_nandf_b uhvio input keeper table 128. 13 x 13 mm signal assignments, power rails, and i/o (continued) contact name contact assignment power rail i/o buffer type direction after reset 1 configuraton after reset 1
package information and contact assignments i.mx51 applications processors for consumer and industrial products, rev. 6 freescale semiconductor 167 nandf_d8 a4 nvcc_nandf_b uhvio input keeper nandf_d9 h6 nvcc_nandf_b uhvio input keeper nandf_rb0 d2 nvcc_nandf_a uhvio input 100 k pull-up nandf_rb1 c1 nvcc_nandf_a uhvio input 100 k pull-up nandf_rb2 d3 nvcc_nandf_a uhvio input 100 k pull-up nandf_rb3 c2 nvcc_nandf_a uhvio input 100 k pull-up nandf_rdy_int d6 nvcc_nandf_b uhvio input 100 k pull-up nandf_re_b f6 nvcc_nandf_a uhvio output ? nandf_we_b g6 nvcc_nandf_a uhvio output ? nandf_wp_b e3 nvcc_nandf_a uhvio output ? owire_line a15 nvcc_per12 gpio input 100 k pull-up pmic_int_req ac18 nvcc_srtc_pow gpio input 100 k pull-up pmic_on_req ae18 nvcc_srtc_pow gpio input 100 k pull-up pmic_rdy ac19 nvcc_srtc_pow gpio input 100 k pull-up pmic_stby_req ab18 nvcc_srtc_pow gpio input 100 k pull-up por_b y24 nvcc_per3 lvio input 100 k pull-up reset_in_b aa25 nvcc_per3 lvio input 100 k pull-up sd1_clk a18 nvcc_per15 uhvio output ? sd1_cmd c17 nvcc_per15 uhvio input 47 k pull-up sd1_data0 b18 nvcc_per15 uhvio input 47 k pull-up sd1_data1 d17 nvcc_per15 uhvio input 47 k pull-up sd1_data2 d18 nvcc_per15 uhvio input 47 k pull-up sd1_data3 c18 nvcc_per15 uhvio input 360 k pull-down sd2_clk a19 nvcc_per17 uhvio output ? sd2_cmd f16 nvcc_per17 uhvio input 47 k pull-up sd2_data0 f18 nvcc_per17 uhvio input 47 k pull-up sd2_data1 b21 nvcc_per17 uhvio input 47 k pull-up sd2_data2 a21 nvcc_per17 uhvio input 47 k pull-up sd2_data3 f17 nvcc_per17 uhvio input 360 k pull-down str d14 nvcc_per12 ? ? ? table 128. 13 x 13 mm signal assignments, power rails, and i/o (continued) contact name contact assignment power rail i/o buffer type direction after reset 1 configuraton after reset 1
i.mx51 applications processors for consumer and industrial products, rev. 6 168 freescale semiconductor package information and contact assignments test_mode ab25 nvcc_per3 gpio input 100 k pull-down uart1_cts b13 nvcc_per12 gpio input 100 k pull-up uart1_rts c13 nvcc_per12 gpio input 100 k pull-up uart1_rxd d13 nvcc_per12 gpio input 100 k pull-up uart1_txd a12 nvcc_per12 gpio input 100 k pull-up uart2_rxd a13 nvcc_per12 gpio input 100 k pull-up uart2_txd c14 nvcc_per12 gpio input 100 k pull-up uart3_rxd b14 nvcc_per12 gpio input keeper uart3_txd a14 nvcc_per12 gpio input keeper usbh1_clk c11 nvcc_per11 gpio input keeper usbh1_data0 b11 nvcc_per11 gpio input keeper usbh1_data1 a10 nvcc_per11 gpio input keeper usbh1_data2 a9 nvcc_per11 gpio input keeper usbh1_data3 c10 nvcc_per11 gpio input keeper usbh1_data4 b9 nvcc_per11 gpio input keeper usbh1_data5 f14 nvcc_per11 gpio input keeper usbh1_data6 c12 nvcc_per11 gpio input keeper usbh1_data7 b12 nvcc_per11 gpio input keeper usbh1_dir b10 nvcc_per11 gpio input keeper usbh1_nxt d12 nvcc_per11 gpio input keeper usbh1_stp a11 nvcc_per11 gpio input keeper xtal 2 ae23 nvcc_osc analog output ? 1 the state immediately after reset and before rom firmware or software has executed. 2 see table 3 on page 12 for more information. 3 during power-on reset this port acts as input for fuse override signal. see table 132 on page 189 for more information. 4 during power-on reset this port acts as output for diagnostic signal. see table 132 on page 189 for more information. table 128. 13 x 13 mm signal assignments, power rails, and i/o (continued) contact name contact assignment power rail i/o buffer type direction after reset 1 configuraton after reset 1
package information and contact assignments i.mx51 applications processors for consumer and industrial products, rev. 6 freescale semiconductor 169 5.1.2.3 13 x 13 mm no connect assignments table 129 shows the device no connect assignment list. table 129. 13 x 13 mm no connect assignments ball status ball assignments nc e5 nc e6 nc e8 nc e9 nc e11 nc e12 nc e14 nc e15 nc e17 nc e18 nc e20 nc e21 nc f5 nc f21 nc g7 nc g8 nc g9 nc g10 nc g11 nc g12 nc g13 nc g14 nc g15 nc g16 nc g17 nc g18 nc g19 nc g21 nc h5 nc h7
i.mx51 applications processors for consumer and industrial products, rev. 6 170 freescale semiconductor package information and contact assignments nc h17 nc h19 nc h21 nc j5 nc j7 nc j17 nc j19 nc j21 nc k7 nc k17 nc k19 nc k21 nc l7 nc l17 nc l19 nc m7 nc m17 nc m19 nc m21 nc n7 nc n17 nc n19 nc n21 nc p5 nc p7 nc p17 nc p19 nc r7 nc r17 nc r19 nc r21 nc t7 nc t17 table 129. 13 x 13 mm no connect assignments (continued) ball status ball assignments
package information and contact assignments i.mx51 applications processors for consumer and industrial products, rev. 6 freescale semiconductor 171 nc t19 nc t21 nc u7 nc u17 nc u19 nc v5 nc v7 nc v19 nc v21 nc w7 nc w8 nc w9 nc w10 nc w11 nc w12 nc w13 nc w14 nc w15 nc w16 nc w17 nc w18 nc w19 nc w21 nc y21 nc aa6 nc aa8 nc aa9 nc aa11 nc aa12 nc aa14 nc aa15 nc aa17 nc aa18 table 129. 13 x 13 mm no connect assignments (continued) ball status ball assignments
i.mx51 applications processors for consumer and industrial products, rev. 6 172 freescale semiconductor package information and contact assignments nc aa20 nc aa21 table 129. 13 x 13 mm no connect assignments (continued) ball status ball assignments
package information and contact assignments i.mx51 applications processors for consumer and industrial products, rev. 6 freescale semiconductor 173 5.1.3 13 x 13 mm ball map see section 5.3, ?13 13 mm, 0.5 pitch ball map . ? 5.2 19 x 19 mm package information this section contains the outline drawing, signal assi gnment map, ground/power/reference id (by ball grid location) for the 19 19 mm, 0.8 mm pitch package.
i.mx51 applications processors for consumer and industrial products, rev. 6 174 freescale semiconductor package information and contact assignments 5.2.1 bga?case 2017, 19 x 19 mm, 0.8 mm pitch figure 110 shows the top view, bottom view, and side view of the 19 19 mm package. figure 110. 19 x 19 mm package: case 2017-01?0.8 mm pitch
package information and contact assignments i.mx51 applications processors for consumer and industrial products, rev. 6 freescale semiconductor 175 5.2.1.1 19 x 19 mm package drawing notes the following notes apply to figure 110 . 1 all dimensions in millimeters. 2 dimensioning and tolerancing per asme y14.5m-1994. 3 maximum solder ball diameter measured parallel to datum a. 4 datum a, the seating plane, is determined by the spherical crowns of the solder balls. 5 parallelism measurement shall exclude any effect of mark on top surface of package. 5.2.2 19 x 19 mm signal assignments, power rails, and i/o table 130 shows the device connection list and table 131 displays an alpha-sorted list of the signal assignments including associated power supplies. 5.2.2.1 19 x 19 mm ground, power, sense, and reference contact assignments table 130 shows the device connection list for ground, power, sense, and reference contact signals alpha-sorted by name. table 130. 19 x 19 mm ground, power, sense, and reference contact assignments contact name contact assignment ahvddrgb y18, aa18 ahvssrgb y19, aa19 gnd a1 , a23, g5, h9, j8, j9, j10, j12, j13, j14, k8, k9, k10, k11, k12, k13, k14, l8, l9, l10, l11,l12, l13, l14, m9, m10, m11, m12, m13, m14, m15, n8, n9, n10, n11, n12, n13, n14, n15, n16, p8, p9, p10, p11, p12, p13, p14, p15, r8, r9, r10, r11,r12, r13, r14, r15, r16, t5, t16, ac1, ac21, ac23 gnd_ana_pll_a u7 gnd_ana_pll_b u17 gnd_dig_pll_a t7 gnd_dig_pll_b v18 ngnd_osc v17 ngnd_tv_back t15 ngnd_usbphy l16 nvcc_emi u8, u9, u10, u11, u12, v7 nvcc_emi_dram h6, j6, k6, l6, m6, n6, p6, r6, t6 nvcc_hs10 m16 nvcc_hs4_1 m18 nvcc_hs4_2 n18 nvcc_hs6 m17 nvcc_i2c t14
i.mx51 applications processors for consumer and industrial products, rev. 6 176 freescale semiconductor package information and contact assignments nvcc_ipu2 t18 nvcc_ipu4 g16 nvcc_ipu5 h17 nvcc_ipu6 j17 nvcc_ipu7 k17 nvcc_ipu8 p18 nvcc_ipu9 r18 nvcc_nandf_a e6, f5 nvcc_nandf_b g9 nvcc_nandf_c g10 nvcc_osc w17 nvcc_per3 u18 nvcc_per5 g15 nvcc_per8 h16 nvcc_per9 h10 nvcc_per10 h11 nvcc_per11 g11 nvcc_per12 g12 nvcc_per13 g13 nvcc_per14 u13 nvcc_per15 h15 nvcc_per17 g14 nvcc_srtc_pow u14 nvcc_tv_back u16 nvcc_usbphy l17 rrefext k19 sgnd j11 svcc h14 svddgp f13 tvdac_dhvdd v16 vbus k20 vcc h13, j15, j16, k15, k16, l7, l15, m7, n7, n17, p7, p17, r17, t8, t9, t10, t11, t12, t17 vdd_ana_pll_a v6 table 130. 19 x 19 mm ground, power, sense, and reference contact assignments (continued) contact name contact assignment
package information and contact assignments i.mx51 applications processors for consumer and industrial products, rev. 6 freescale semiconductor 177 5.2.2.2 19 x 19 mm, signal assignments, power rails, and i/o table 131 displays an alpha-sorted list of the signal assignments including power rails. vdd_ana_pll_b w19 vdd_dig_pll_a u6 vdd_dig_pll_b w18 vdd_fuse r7 vdda g8, h8, h12, m8, p16, t13 vdda33 l18 vddgp f6, f7, f8, f9, f10, f11, f12, g6, g7, h7, j7, k7 vrefout u15 vref r5 vreg k21 table 131. 19 x 19 mm signal assignments, power rails, and i/o contact name contact assignment power rail i/o buffer type direction after reset 1 configuraton after reset 1 aud3_bb_ck c8 nvcc_per9 gpio input keeper aud3_bb_fs a9 nvcc_per9 gpio input keeper aud3_bb_rxd b9 nvcc_per9 gpio input keeper aud3_bb_txd e9 nvcc_per9 gpio input keeper boot_mode0 ab21 nvcc_per3 lvio input 100 k pull-up boot_mode1 ab22 nvcc_per3 lvio input 100 k pull-up ckih1 v19 nvcc_per3 analog input analog ckih2 aa20 nvcc_per3 analog input analog ckil y16 nvcc_srtc_pow gpio input standard cmos clk_ss aa21 nvcc_per3 lvio input 100 k pull-up comp 2 y17 ahvddrgb analog input analog csi1_d10 r22 nvcc_hs10 hsgpio input keeper csi1_d11 r23 nvcc_hs10 hsgpio input keeper csi1_d12 p22 nvcc_hs10 hsgpio input keeper csi1_d13 p23 nvcc_hs10 hsgpio input keeper csi1_d14 m20 nvcc_hs10 hsgpio input keeper table 130. 19 x 19 mm ground, power, sense, and reference contact assignments (continued) contact name contact assignment
i.mx51 applications processors for consumer and industrial products, rev. 6 178 freescale semiconductor package information and contact assignments csi1_d15 m21 nvcc_hs10 hsgpio input keeper csi1_d16 n22 nvcc_hs10 hsgpio input keeper csi1_d17 n23 nvcc_hs10 hsgpio input keeper csi1_d18 m22 nvcc_hs10 hsgpio input keeper csi1_d19 m23 nvcc_hs10 hsgpio input keeper csi1_d8 e18 nvcc_per8 gpio input keeper csi1_d9 a21 nvcc_per8 gpio input keeper csi1_hsync a20 nvcc_per8 gpio input keeper csi1_mclk b20 nvcc_per8 gpio input keeper csi1_pixclk f18 nvcc_per8 gpio input keeper csi1_vsync g18 nvcc_per8 gpio input keeper csi2_d12 b8 nvcc_per9 gpio input keeper csi2_d13 c7 nvcc_per9 gpio input keeper csi2_d14 l20 nvcc_hs4_1 hsgpio input keeper csi2_d15 l21 nvcc_hs4_1 hsgpio input keeper csi2_d16 l22 nvcc_hs4_1 hsgpio input keeper csi2_d17 l23 nvcc_hs4_1 hsgpio input keeper csi2_d18 d9 nvcc_per9 gpio input keeper csi2_d19 a8 nvcc_per9 gpio input keeper csi2_hsync c18 nvcc_per8 gpio input keeper csi2_pixclk e19 nvcc_per8 gpio input keeper csi2_vsync f19 nvcc_per8 gpio input keeper cspi1_miso c10 nvcc_per10 gpio input 100 k pull-up cspi1_mosi d10 nvcc_per10 gpio input 100 k pull-up cspi1_rdy c9 nvcc_per10 gpio input keeper cspi1_sclk a10 nvcc_per10 gpio input 100 k pull-up cspi1_ss0 e10 nvcc_per10 gpio input 100 k pull-up cspi1_ss1 b10 nvcc_per10 gpio input 100 k pull-up di_gp1 h21 nvcc_ipu6 gpio input keeper di_gp2 j19 nvcc_ipu6 gpio input keeper di_gp3 h22 nvcc_ipu7 gpio input 100 k pull-up di_gp4 j22 nvcc_ipu7 gpio input 100 k pull-up table 131. 19 x 19 mm signal assignments, power rails, and i/o (continued) contact name contact assignment power rail i/o buffer type direction after reset 1 configuraton after reset 1
package information and contact assignments i.mx51 applications processors for consumer and industrial products, rev. 6 freescale semiconductor 179 di1_d0_cs u21 nvcc_ipu2 gpio output high di1_d1_cs ab23 nvcc_ipu2 gpio output high di1_disp_clk j18 nvcc_ipu6 gpio output low di1_pin11 y22 nvcc_ipu2 gpio output high di1_pin12 aa22 nvcc_ipu2 gpio output high di1_pin13 t20 nvcc_ipu2 gpio output high di1_pin15 h20 nvcc_ipu6 gpio output high di1_pin2 g23 nvcc_ipu6 gpio output high di1_pin3 g22 nvcc_ipu6 gpio output high di2_disp_clk j21 nvcc_ipu7 gpio output high di2_pin2 j20 nvcc_ipu7 gpio output high di2_pin3 k18 nvcc_ipu7 gpio output high di2_pin4 h23 nvcc_ipu7 gpio input keeper disp1_dat0 n20 nvcc_hs6 hsgpio input keeper disp1_dat1 n21 nvcc_hs6 hsgpio input keeper disp1_dat10 3 d22 nvcc_ipu4 gpio input keeper disp1_dat11 3 d23 nvcc_ipu4 gpio input keeper disp1_dat12 3 e21 nvcc_ipu4 gpio input keeper disp1_dat13 3 f20 nvcc_ipu4 gpio input keeper disp1_dat14 3 e22 nvcc_ipu4 gpio input keeper disp1_dat15 3 g19 nvcc_ipu4 gpio input keeper disp1_dat16 3 e23 nvcc_ipu5 gpio input keeper disp1_dat17 3 f21 nvcc_ipu5 gpio input keeper disp1_dat18 3 g20 nvcc_ipu5 gpio input keeper disp1_dat19 3 h18 nvcc_ipu5 gpio input keeper disp1_dat2 u22 nvcc_hs6 hsgpio input keeper disp1_dat20 3 f23 nvcc_ipu5 gpio input keeper disp1_dat21 3 h19 nvcc_ipu5 gpio input keeper disp1_dat22 3 f22 nvcc_ipu5 gpio input keeper disp1_dat23 3 g21 nvcc_ipu5 gpio input keeper disp1_dat3 u23 nvcc_hs6 hsgpio input keeper disp1_dat4 t22 nvcc_hs6 hsgpio input keeper table 131. 19 x 19 mm signal assignments, power rails, and i/o (continued) contact name contact assignment power rail i/o buffer type direction after reset 1 configuraton after reset 1
i.mx51 applications processors for consumer and industrial products, rev. 6 180 freescale semiconductor package information and contact assignments disp1_dat5 t23 nvcc_hs6 hsgpio input keeper disp1_dat6 3 c22 nvcc_ipu4 gpio input keeper disp1_dat7 3 c23 nvcc_ipu4 gpio input keeper disp1_dat8 3 d21 nvcc_ipu4 gpio input keeper disp1_dat9 3 e20 nvcc_ipu4 gpio input keeper disp2_dat0 r21 nvcc_ipu8 gpio input keeper disp2_dat1 m19 nvcc_ipu8 gpio input keeper disp2_dat10 w22 nvcc_ipu9 gpio input keeper disp2_dat11 r19 nvcc_ipu9 gpio input keeper disp2_dat12 y23 nvcc_ipu9 gpio input keeper disp2_dat13 t19 nvcc_ipu9 gpio input keeper disp2_dat14 aa23 nvcc_ipu9 gpio input keeper disp2_dat15 t21 nvcc_ipu9 gpio input keeper disp2_dat2 p20 nvcc_hs4_2 hsgpio input keeper disp2_dat3 p21 nvcc_hs4_2 hsgpio input keeper disp2_dat4 v22 nvcc_hs4_2 hsgpio input keeper disp2_dat5 v23 nvcc_hs4_2 hsgpio input keeper disp2_dat6 n19 nvcc_ipu8 gpio input keeper disp2_dat7 w23 nvcc_ipu8 gpio input keeper disp2_dat8 p19 nvcc_ipu9 gpio input keeper disp2_dat9 r20 nvcc_ipu9 gpio input keeper dispb2_ser_clk ac22 nvcc_ipu2 gpio output high dispb2_ser_din u19 nvcc_ipu2 gpio input 100 k pull-up dispb2_ser_dio v21 nvcc_ipu2 gpio input 100 k pull-up dispb2_ser_rs w21 nvcc_ipu2 gpio output high dn k22 vdda33 analog output ? dp k23 vdda33 analog output ? dram_a0 ab1 nvcc_emi_dram ddr2 output high dram_a1 aa2 nvcc_emi_dram ddr2 output high dram_a10 v2 nvcc_emi_dram ddr2 output high dram_a11 u4 nvcc_emi_dram ddr2 output high dram_a12 u2 nvcc_emi_dram ddr2 output high table 131. 19 x 19 mm signal assignments, power rails, and i/o (continued) contact name contact assignment power rail i/o buffer type direction after reset 1 configuraton after reset 1
package information and contact assignments i.mx51 applications processors for consumer and industrial products, rev. 6 freescale semiconductor 181 dram_a13 u1 nvcc_emi_dram ddr2 output high dram_a14 t2 nvcc_emi_dram ddr2 output high dram_a2 aa3 nvcc_emi_dram ddr2 output high dram_a3 v5 nvcc_emi_dram ddr2 output high dram_a4 w4 nvcc_emi_dram ddr2 output high dram_a5 y2 nvcc_emi_dram ddr2 output high dram_a6 w3 nvcc_emi_dram ddr2 output high dram_a7 y1 nvcc_emi_dram ddr2 output high dram_a8 w2 nvcc_emi_dram ddr2 output high dram_a9 v3 nvcc_emi_dram ddr2 output high dram_cas v4 nvcc_emi_dram ddr2 output high dram_cs0 y4 nvcc_emi_dram ddr2 output high dram_cs1 y3 nvcc_emi_dram ddr2 output high dram_d0 t1 nvcc_emi_dram ddr2 output high dram_d1 r3 nvcc_emi_dram ddr2 output high dram_d10 m3 nvcc_emi_dram ddr2 output high dram_d11 m4 nvcc_emi_dram ddr2 output high dram_d12 m1 nvcc_emi_dram ddr2 output high dram_d13 m5 nvcc_emi_dram ddr2 output high dram_d14 l5 nvcc_emi_dram ddr2 output high dram_d15 l4 nvcc_emi_dram ddr2 output high dram_d16 l3 nvcc_emi_dram ddr2 output high dram_d17 l2 nvcc_emi_dram ddr2 output high dram_d18 l1 nvcc_emi_dram ddr2 output high dram_d19 k1 nvcc_emi_dram ddr2 output high dram_d2 r2 nvcc_emi_dram ddr2 output high dram_d20 k3 nvcc_emi_dram ddr2 output high dram_d21 k4 nvcc_emi_dram ddr2 output high dram_d22 j3 nvcc_emi_dram ddr2 output high dram_d23 j4 nvcc_emi_dram ddr2 output high dram_d24 k5 nvcc_emi_dram ddr2 output high dram_d25 h1 nvcc_emi_dram ddr2 output high table 131. 19 x 19 mm signal assignments, power rails, and i/o (continued) contact name contact assignment power rail i/o buffer type direction after reset 1 configuraton after reset 1
i.mx51 applications processors for consumer and industrial products, rev. 6 182 freescale semiconductor package information and contact assignments dram_d26 h2 nvcc_emi_dram ddr2 output high dram_d27 j5 nvcc_emi_dram ddr2 output high dram_d28 g1 nvcc_emi_dram ddr2 output high dram_d29 g2 nvcc_emi_dram ddr2 output high dram_d3 r1 nvcc_emi_dram ddr2 output high dram_d30 g3 nvcc_emi_dram ddr2 output high dram_d31 g4 nvcc_emi_dram ddr2 output high dram_d4 r4 nvcc_emi_dram ddr2 output high dram_d5 p5 nvcc_emi_dram ddr2 output high dram_d6 p4 nvcc_emi_dram ddr2 output high dram_d7 n5 nvcc_emi_dram ddr2 output high dram_d8 n2 nvcc_emi_dram ddr2 output high dram_d9 n1 nvcc_emi_dram ddr2 output high dram_dqm0 p3 nvcc_emi_dram ddr2 output high dram_dqm1 m2 nvcc_emi_dram ddr2 output high dram_dqm2 k2 nvcc_emi_dram ddr2 output high dram_dqm3 h5 nvcc_emi_dram ddr2 output high dram_ras w1 nvcc_emi_dram ddr2 output high dram_sdcke0 aa1 nvcc_emi_dram ddr2 output high dram_sdcke1 w5 nvcc_emi_dram ddr2 output high dram_sdclk t3 nvcc_emi_dram ddr2clk output high dram_sdclk_b t4 nvcc_emi_dram ddr2clk output high dram_sdqs0 p2 nvcc_emi_dram ddr2clk output high dram_sdqs0_b p1 nvcc_emi_dram ddr2clk output high dram_sdqs1 n4 nvcc_emi_dram ddr2clk output high dram_sdqs1_b n3 nvcc_emi_dram ddr2clk output high dram_sdqs2 j1 nvcc_emi_dram ddr2clk output high dram_sdqs2_b j2 nvcc_emi_dram ddr2clk output high dram_sdqs3 h3 nvcc_emi_dram ddr2clk output high dram_sdqs3_b h4 nvcc_emi_dram ddr2clk output high dram_sdwe u5 nvcc_emi_dram ddr2 output high eim_a16 3 aa9 nvcc_emi gpio input 100 k pull-up table 131. 19 x 19 mm signal assignments, power rails, and i/o (continued) contact name contact assignment power rail i/o buffer type direction after reset 1 configuraton after reset 1
package information and contact assignments i.mx51 applications processors for consumer and industrial products, rev. 6 freescale semiconductor 183 eim_a17 3 ab9 nvcc_emi gpio input 100 k pull-up eim_a18 3 ac8 nvcc_emi gpio input 100 k pull-up eim_a19 3 aa8 nvcc_emi gpio input 100 k pull-up eim_a20 3 ab8 nvcc_emi gpio input 100 k pull-up eim_a21 3 ac7 nvcc_emi gpio input 100 k pull-up eim_a22 ab7 nvcc_emi gpio output high eim_a23 3 ac6 nvcc_emi gpio input 100 k pull-up eim_a24 ac5 nvcc_emi gpio input 100 k pull-up eim_a25 ab6 nvcc_emi gpio input 100 k pull-up eim_a26 ac4 nvcc_emi gpio input 100 k pull-up eim_a27 ab5 nvcc_emi gpio input keeper eim_bclk aa4 nvcc_emi gpio input keeper eim_cre ab2 nvcc_emi gpio output high eim_cs0 w6 nvcc_emi gpio output high eim_cs1 y6 nvcc_emi gpio output high eim_cs2 y7 nvcc_emi gpio input keeper eim_cs3 ac3 nvcc_emi gpio input keeper eim_cs4 aa6 nvcc_emi gpio input keeper eim_cs5 aa5 nvcc_emi gpio input keeper eim_d16 ac12 nvcc_emi gpio input keeper eim_d17 w10 nvcc_emi gpio input keeper eim_d18 aa11 nvcc_emi gpio input keeper eim_d19 y10 nvcc_emi gpio input keeper eim_d20 ab11 nvcc_emi gpio input keeper eim_d21 w9 nvcc_emi gpio input keeper eim_d22 ac11 nvcc_emi gpio input keeper eim_d23 v8 nvcc_emi gpio input keeper eim_d24 aa10 nvcc_emi gpio input keeper eim_d25 y9 nvcc_emi gpio input keeper eim_d26 ab10 nvcc_emi gpio input keeper eim_d27 w8 nvcc_emi gpio input keeper eim_d28 ac10 nvcc_emi gpio input keeper table 131. 19 x 19 mm signal assignments, power rails, and i/o (continued) contact name contact assignment power rail i/o buffer type direction after reset 1 configuraton after reset 1
i.mx51 applications processors for consumer and industrial products, rev. 6 184 freescale semiconductor package information and contact assignments eim_d29 y8 nvcc_emi gpio input keeper eim_d30 ac9 nvcc_emi gpio input keeper eim_d31 w7 nvcc_emi gpio input keeper eim_da0 ac15 nvcc_emi gpio input keeper eim_da1 v13 nvcc_emi gpio input keeper eim_da10 ac13 nvcc_emi gpio input keeper eim_da11 v11 nvcc_emi gpio input keeper eim_da12 aa12 nvcc_emi gpio input keeper eim_da13 w11 nvcc_emi gpio input keeper eim_da14 ab12 nvcc_emi gpio input keeper eim_da15 y11 nvcc_emi gpio input keeper eim_da2 aa14 nvcc_emi gpio input keeper eim_da3 ab14 nvcc_emi gpio input keeper eim_da4 ac14 nvcc_emi gpio input keeper eim_da5 y13 nvcc_emi gpio input keeper eim_da6 aa13 nvcc_emi gpio input keeper eim_da7 w13 nvcc_emi gpio input keeper eim_da8 ab13 nvcc_emi gpio input keeper eim_da9 y12 nvcc_emi gpio input keeper eim_dtack y5 nvcc_emi gpio input 100 k pull-up eim_eb0 v12 nvcc_emi gpio output high eim_eb1 w12 nvcc_emi gpio output high eim_eb2 v10 nvcc_emi gpio input keeper eim_eb3 v9 nvcc_emi gpio input keeper eim_lba ac2 nvcc_emi gpio output high eim_oe aa7 nvcc_emi gpio output high eim_rw ab3 nvcc_emi gpio output high eim_sdba0 v1 nvcc_emi_dram ddr2 output high eim_sdba1 u3 nvcc_emi_dram ddr2 output high eim_sdba2 f1 nvcc_emi_dram ddr2 output high eim_sdodt0 f3 nvcc_emi_dram ddr2 output high eim_sdodt1 f2 nvcc_emi_dram ddr2 output high table 131. 19 x 19 mm signal assignments, power rails, and i/o (continued) contact name contact assignment power rail i/o buffer type direction after reset 1 configuraton after reset 1
package information and contact assignments i.mx51 applications processors for consumer and industrial products, rev. 6 freescale semiconductor 185 eim_wait ab4 nvcc_emi gpio input 100 k pull-up extal 2 ab20 nvcc_osc analog input ? fastr_ana 2 w20 nvcc_per3 ? input ? fastr_dig 2 y20 nvcc_per3 ? input ? gpanaio 2 j23 nvcc_usbphy analog output ? gpio_nand d5 nvcc_nandf_a uhvio input 100 k pull-up gpio1_0 b21 nvcc_per5 gpio input keeper gpio1_1 d20 nvcc_per5 gpio input keeper gpio1_2 a22 nvcc_per5 gpio input keeper gpio1_3 d18 nvcc_per5 gpio input keeper gpio1_4 b22 nvcc_per5 gpio input keeper gpio1_5 d19 nvcc_per5 gpio input keeper gpio1_6 c19 nvcc_per5 gpio input keeper gpio1_7 b23 nvcc_per5 gpio input keeper gpio1_8 c21 nvcc_per5 gpio input keeper gpio1_9 c20 nvcc_per5 gpio input keeper i2c1_clk w15 nvcc_i2c i2cio input 47 k pull-up i2c1_dat ab16 nvcc_i2c i2cio input 47 k pull-up id l19 nvcc_usbphy analog input pull-up iob 2 ac19 ahvddrgb analog output ? iob_back 2 ab19 ? analog output ? iog 2 ac18 ahvddrgb analog output ? iog_back 2 ab18 ? analog output ? ior 2 ac17 ahvddrgb analog output ? ior_back 2 ab17 ? analog output ? jtag_de_b ab15 nvcc_per14 gpio input/open-drain output 47 k pull-up jtag_mod v14 nvcc_per14 gpio input 100 k pull-up jtag_tck v15 nvcc_per14 gpio input 100 k pull-down jtag_tdi y14 nvcc_per14 gpio input 47 k pull-up jtag_tdo aa15 nvcc_per14 gpio 3-state output keeper jtag_tms ac16 nvcc_per14 gpio input 47 k pull-up table 131. 19 x 19 mm signal assignments, power rails, and i/o (continued) contact name contact assignment power rail i/o buffer type direction after reset 1 configuraton after reset 1
i.mx51 applications processors for consumer and industrial products, rev. 6 186 freescale semiconductor package information and contact assignments jtag_trstb w14 nvcc_per14 gpio input 47 k pull-up key_col0 e15 nvcc_per13 gpio input 100 k pull-up key_col1 a16 nvcc_per13 gpio input 100 k pull-up key_col2 d15 nvcc_per13 gpio input 100 k pull-up key_col3 4 b17 nvcc_per13 gpio output high key_col4 4 f16 nvcc_per13 gpio output low key_col5 4 c16 nvcc_per13 gpio output low key_row0 d14 nvcc_per13 gpio input 100 k pull-up key_row1 b16 nvcc_per13 gpio input 100 k pull-up key_row2 f15 nvcc_per13 gpio input 100 k pull-up key_row3 c15 nvcc_per13 gpio input 100 k pull-up nandf_ale e3 nvcc_nandf_a uhvio output high nandf_cle f4 nvcc_nandf_a uhvio output high nandf_cs0 c3 nvcc_nandf_a uhvio output high nandf_cs1 c2 nvcc_nandf_a uhvio output high nandf_cs2 e4 nvcc_nandf_a uhvio output high nandf_cs3 b1 nvcc_nandf_a uhvio output high nandf_cs4 b2 nvcc_nandf_a uhvio output low nandf_cs5 a2 nvcc_nandf_a uhvio output low nandf_cs6 e5 nvcc_nandf_b uhvio output low nandf_cs7 c4 nvcc_nandf_b uhvio output low nandf_d0 a7 nvcc_nandf_c uhvio input keeper nandf_d1 e8 nvcc_nandf_c uhvio input keeper nandf_d10 b5 nvcc_nandf_b uhvio input keeper nandf_d11 d7 nvcc_nandf_b uhvio input keeper nandf_d12 c5 nvcc_nandf_b uhvio input keeper nandf_d13 a3 nvcc_nandf_b uhvio input keeper nandf_d14 b4 nvcc_nandf_b uhvio input keeper nandf_d15 d6 nvcc_nandf_b uhvio input keeper nandf_d2 a6 nvcc_nandf_c uhvio input keeper nandf_d3 d8 nvcc_nandf_c uhvio input keeper nandf_d4 b7 nvcc_nandf_c uhvio input keeper table 131. 19 x 19 mm signal assignments, power rails, and i/o (continued) contact name contact assignment power rail i/o buffer type direction after reset 1 configuraton after reset 1
package information and contact assignments i.mx51 applications processors for consumer and industrial products, rev. 6 freescale semiconductor 187 nandf_d5 a5 nvcc_nandf_c uhvio input keeper nandf_d6 b6 nvcc_nandf_c uhvio input keeper nandf_d7 c6 nvcc_nandf_b uhvio input keeper nandf_d8 a4 nvcc_nandf_b uhvio input keeper nandf_d9 e7 nvcc_nandf_b uhvio input keeper nandf_rb0 d2 nvcc_nandf_a uhvio input 100 k pull-up nandf_rb1 d4 nvcc_nandf_a uhvio input 100 k pull-up nandf_rb2 d3 nvcc_nandf_a uhvio input 100 k pull-up nandf_rb3 c1 nvcc_nandf_a uhvio input 100 k pull-up nandf_rdy_int b3 nvcc_nandf_b uhvio input 100 k pull-up nandf_re_b e2 nvcc_nandf_a uhvio output ? nandf_we_b e1 nvcc_nandf_a uhvio output ? nandf_wp_b d1 nvcc_nandf_a uhvio output ? owire_line e14 nvcc_per12 gpio input 100 k pull-up pmic_int_req aa16 nvcc_srtc_pow gpio input 100 k pull-up pmic_on_req w16 nvcc_srtc_pow gpio input 100 k pull-up pmic_rdy aa17 nvcc_srtc_pow gpio input 100 k pull-up pmic_stby_req y15 nvcc_srtc_pow gpio input 100 k pull-up por_b u20 nvcc_per3 lvio input 100 k pull-up reset_in_b y21 nvcc_per3 lvio input 100 k pull-up sd1_clk a17 nvcc_per15 uhvio output ? sd1_cmd e16 nvcc_per15 uhvio input 47 k pull-up sd1_data0 d16 nvcc_per15 uhvio input 47 k pull-up sd1_data1 a18 nvcc_per15 uhvio input 47 k pull-up sd1_data2 f17 nvcc_per15 uhvio input 47 k pull-up sd1_data3 a19 nvcc_per15 uhvio input 360 k pull-down sd2_clk b18 nvcc_per17 uhvio output ? sd2_cmd g17 nvcc_per17 uhvio input 47 k pull-up sd2_data0 e17 nvcc_per17 uhvio input 47 k pull-up sd2_data1 b19 nvcc_per17 uhvio input 47 k pull-up sd2_data2 d17 nvcc_per17 uhvio input 47 k pull-up sd2_data3 c17 nvcc_per17 uhvio input 360 k pull-down table 131. 19 x 19 mm signal assignments, power rails, and i/o (continued) contact name contact assignment power rail i/o buffer type direction after reset 1 configuraton after reset 1
i.mx51 applications processors for consumer and industrial products, rev. 6 188 freescale semiconductor package information and contact assignments str a15 nvcc_per12 ? ? ? test_mode v20 nvcc_per3 gpio input 100 k pull-down uart1_cts b14 nvcc_per12 gpio input 100 k pull-up uart1_rts d13 nvcc_per12 gpio input 100 k pull-up uart1_rxd e13 nvcc_per12 gpio input 100 k pull-up uart1_txd a13 nvcc_per12 gpio input 100 k pull-up uart2_rxd a14 nvcc_per12 gpio input 100 k pull-up uart2_txd c14 nvcc_per12 gpio input 100 k pull-up uart3_rxd f14 nvcc_per12 gpio input keeper uart3_txd b15 nvcc_per12 gpio input keeper usbh1_clk d11 nvcc_per11 gpio input keeper usbh1_data0 e12 nvcc_per11 gpio input keeper usbh1_data1 a11 nvcc_per11 gpio input keeper usbh1_data2 b12 nvcc_per11 gpio input keeper usbh1_data3 c12 nvcc_per11 gpio input keeper usbh1_data4 d12 nvcc_per11 gpio input keeper usbh1_data5 a12 nvcc_per11 gpio input keeper usbh1_data6 b13 nvcc_per11 gpio input keeper usbh1_data7 c13 nvcc_per11 gpio input keeper usbh1_dir b11 nvcc_per11 gpio input keeper usbh1_nxt c11 nvcc_per11 gpio input keeper usbh1_stp e11 nvcc_per11 gpio input keeper xtal 2 ac20 nvcc_osc analog output ? 1 the state immediately after reset and before rom firmware or software has executed. 2 see table 3 on page 12 for more information. 3 during power-on reset this port acts as input for fuse override signal. see table 132 on page 189 for more information. 4 during power-on reset this port acts as output for diagnostic signal. see table 132 on page 189 for more information. table 131. 19 x 19 mm signal assignments, power rails, and i/o (continued) contact name contact assignment power rail i/o buffer type direction after reset 1 configuraton after reset 1
package information and contact assignments i.mx51 applications processors for consumer and industrial products, rev. 6 freescale semiconductor 189 5.2.2.3 fuse override considerations table 132 lists the contacts that can be overridden with fuse settings. table 132. fuse override contacts contact name direction after reset configuration after reset signal configuration 1 external termination for fuse override disp1_dat10 input keeper bt_spare_size 4.7 k pull-up or pull-down disp1_dat11 input keeper bt_lpb_freq[2] 4.7 k pull-up or pull-down disp1_dat12 input keeper bt_mlc_sel 4.7 k pull-up or pull-down disp1_dat13 input keeper bt_mem_ctl[0] 4.7 k pull-up or pull-down disp1_dat14 input keeper bt_mem_ctl[1] 4.7 k pull-up or pull-down disp1_dat15 input keeper bt_bus_width 4.7 k pull-up or pull-down disp1_dat16 input keeper bt_page_size[0] 4.7 k pull-up or pull-down disp1_dat17 input keeper bt_page_size[1] 4.7 k pull-up or pull-down disp1_dat18 input keeper bt_weim_muxed[0] 4.7 k pull-up or pull-down disp1_dat19 input keeper bt_weim_muxed[1] 4.7 k pull-up or pull-down disp1_dat20 input keeper bt_mem_type[0] 4.7 k pull-up or pull-down disp1_dat21 input keeper bt_mem_type[1] 4.7 k pull-up or pull-down disp1_dat22 input keeper bt_lpb_freq[0] 4.7 k pull-up or pull-down disp1_dat23 input keeper bt_lpb_freq[1] 4.7 k pull-up or pull-down disp1_dat6 input keeper bt_usb_src 2 4.7 k pull-up or pull-down disp1_dat7 input keeper bt_eeprom_cfg 4.7 k pull-up or pull-down disp1_dat8 input keeper bt_src[0] 4.7 k pull-up or pull-down disp1_dat9 input keeper bt_src[1] 4.7 k pull-up or pull-down eim_a16 input 100 k pull-up osc_freq_sel[0] 4.7 k pull-down or none for high level 3 eim_a17 input 100 k pull-up osc_freq_sel[1] 4.7 k pull-down or none for high level 2 eim_a18 input 100 k pull-up bt_lpb[0] 4.7 k pull-down or none for high level 2 eim_a19 input 100 k pull-up bt_lpb[1] 4.7 k pull-down or none for high level 2 eim_a20 input 100 k pull-up bt_uart_src[0] 4.7 k pull-down or none for high level 2 eim_a21 input 100 k pull-up bt_uart_src[1] 4.7 k pull-down or none for high level 2 key_col3 output high output for diagnostic signal int_boot during power-on reset ?
i.mx51 applications processors for consumer and industrial products, rev. 6 190 freescale semiconductor package information and contact assignments 5.2.3 19 x 19 ball map see section 5.4, ?19 x 19 mm, 0.8 pitch ball map . ? key_col4 output low output for diagnostic signal any_pu_rst during power-on reset ? key_col5 output low output for diagnostic signal jtag_act during power-on reset ? 1 signal configuration as fuse override input at power up. these are special i/o lines that control the boot up configuration during product development. in production, the boot configuration is controlled by fuses. 2 external usb phy selection is not functional. 3 consider using an external 68 k pull-up if system constraints indicate that the on-chip 100 k pull-up is too weak. table 132. fuse override contacts (continued) contact name direction after reset configuration after reset signal configuration 1 external termination for fuse override
package information and contact assignments i.mx51 applications processors for consumer and industrial products, rev. 6 freescale semiconductor 191 5.3 13 13 mm, 0.5 pitch ball map table 133 shows the 13 x 13 mm, 0.5 pitch ball map. table 133. 13 13 mm, 0.5 mm pitch ball map 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 a gnd nandf_cs6 nandf_d12 nandf_d8 nandf_d7 nandf_d6 csi2_d18 cspi1_rdy usbh1_data2 usbh1_data1 usbh1_stp uart1_txd uart2_rxd uart3_txd owire_line key_col3 key_col5 sd1_clk sd2_clk csi1_d8 sd2_data2 gpio1_3 gpio1_7 gnd gnd a b gnd nandf_cs3 nandf_cs4 nandf_d11 nandf_d3 nandf_d4 aud3_bb_txd aud3_bb_rxd usbh1_data4 usbh1_dir usbh1_data0 usbh1_data7 uart1_cts uart3_rxd key_row0 key_col0 key_col4 sd1_data0 csi1_vsync csi1_d9 sd2_data1 gpio1_4 gpio1_2 gpio1_6 gnd b c nandf_rb1 nandf_rb3 gpio_nand nandf_cs5 nandf_d10 nandf_d2 csi2_d19 aud3_bb_fs aud3_bb_ck usbh1_data3 usbh1_clk usbh1_data6 uart1_rts uart2_txd key_row1 key_col1 sd1_cmd sd1_data3 csi1_hsync csi2_vsync gpio1_1 gpio1_5 disp1_dat8 gpio1_8 gpio1_9 c d nandf_cs1 nandf_rb0 nandf_rb2 nandf_cs0 nandf_cs2 nandf_rdy_int nandf_d0 csi2_d13 cspi1_mosi cspi1_ss0 cspi1_sclk usbh1_nxt uart1_rxd str key_row3 key_col2 sd1_data1 sd1_data2 csi1_pixclk nvcc_per5 csi2_pixclk disp1_dat14 disp1_dat9 disp1_dat7 disp1_dat6 d e nandf_ale nandf_cle nandf_wp_b nandf_d14 ? ? gnd ? ? vddgp ? ? gnd ? ? gnd ? ? gnd ? ? disp1_dat12 disp1_dat13 disp1_dat10 disp1_dat11 e f dram_d31 dram_d16 dram_d17 dram_d19 ? nandf_re_b nandf_cs7 nandf_d5 nandf_d1 nandf_d13 csi2_d12 cspi1_miso cspi1_ss1 usbh1_data5 key_row2 sd2_cmd sd2_data3 sd2_data0 csi1_mclk di_gp1 ? disp1_dat15 disp1_dat16 disp1_dat17 disp1_dat21 f g dram_d29 dram_d30 dram_d18 dram_d21 gnd nandf_we_b ? ? ? ? ? ? ? ? ? ? ? ? ? di1_pin15 ? disp1_dat19 disp1_dat18 disp1_dat22 disp1_dat20 g 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
i.mx51 applications processors for consumer and industrial products, rev. 6 192 freescale semiconductor package information and contact assignments h dram_d27 dram_d28 dram_d20 dram_d23 ? nandf_d9 ? nvcc_nandf_b nvcc_nandf_c nvcc_per9 nvcc_per11 nvcc_per10 vdda nvcc_per13 nvcc_per12 nvcc_per15 ? gpio1_0 ? di1_pin3 ? nvcc_ipu7 di_gp3 di2_pin2 disp1_dat23 h j dram_d25 dram_d26 dram_d22 dram_d24 ? nandf_d15 ? nvcc_nandf_a vddgp vddgp vddgp vddgp gnd gnd nvcc_per8 nvcc_per17 ? di1_pin2 ? csi2_hsync ? di1_disp_clk di2_pin4 di2_disp_clk di2_pin3 j k dram_sdqs3_b dram_sdqs3 dram_sdqs2 dram_sdqs2_b gnd eim_sdba2 ? vddgp vddgp vddgp vddgp vddgp gnd gnd gnd nvcc_ipu5 ? rrefext ? di_gp2 ? gpanaio di_gp4 dp dn k l dram_sdcke1 eim_sdodt0 eim_sdodt1 eim_sdba1 nvcc_emi_dram vddgp ? vddgp vddgp vddgp vddgp vddgp gnd gnd gnd nvcc_ipu9 ? disp2_dat8 ? nvcc_hs4_1 gnd vbus ngnd_usbphy vreg id l m dram_sdclk dram_sdclk_b dram_sdwe dram_dqm2 nvcc_emi_dram vddgp ? vddgp vddgp vddgp svddgp gnd gnd gnd gnd nvcc_ipu6 ? disp2_dat12 ? nvcc_hs10 ? csi2_d17 csi2_d16 csi2_d15 csi2_d14 m n dram_sdcke0 dram_dqm3 dram_ras dram_cas gnd gnd ? gnd gnd gnd gnd vcc svcc vcc vcc nvcc_ipu4 ? vdda ? nvcc_hs6 ? csi1_d19 csi1_d18 csi1_d16 csi1_d17 n p dram_a9 dram_a12 dram_cs0 eim_sdba0 ? vdd_fuse ? gnd gnd sgnd gnd vcc vcc vcc vcc nvcc_usbphy ? disp2_dat1 ? nvcc_hs4_2 gnd csi1_d12 csi1_d13 csi1_d14 csi1_d15 p table 133. 13 13 mm, 0.5 mm pitch ball map (continued) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
package information and contact assignments i.mx51 applications processors for consumer and industrial products, rev. 6 freescale semiconductor 193 r dram_a11 dram_a14 dram_cs1 dram_a13 nvcc_emi_dram vdda ? gnd gnd gnd gnd gnd vcc vcc vcc vdda33 ? disp2_dat10 ? disp2_dat6 ? disp1_dat5 disp1_dat4 csi1_d10 csi1_d11 r t dram_a6 dram_a7 dram_a8 dram_a10 nvcc_emi_dram vdda ? gnd gnd gnd gnd gnd gnd vcc vcc vcc ? di1_d1_cs ? disp2_dat0 ? disp1_dat1 disp1_dat0 disp1_dat2 disp1_dat3 t u dram_a4 dram_a5 dram_a3 dram_a2 gnd vref ? nvcc_emi gnd gnd gnd gnd gnd vcc vcc vcc ? disp2_dat13 ? disp2_dat14 gnd disp2_dat2 disp2_dat3 disp2_dat4 disp2_dat5 u v dram_dqm0 dram_dqm1 dram_a1 dram_a0 ? eim_cre ? nvcc_emi nvcc_per14 nvcc_per3 nvcc_i2c nvcc_srtc_pow ahvssrgb ahvssrgb ahvddrgb ahvddrgb disp2_dat9 di1_pin11 ? nvcc_ipu2 ? nvcc_ipu8 disp2_dat15 disp2_dat11 disp2_dat7 v w dram_sdqs1_b dram_sdqs1 dram_sdqs0 dram_sdqs0_b gnd eim_cs1 ? ? ? ? ? ? ? ? ? ? ? ? ? di1_d0_cs ? boot_mode0 dispb2_ser_rs di1_pin13 di1_pin12 w y dram_d8 dram_d9 dram_d6 dram_d7 nvcc_emi_dram eim_a20 eim_cs5 eim_cs3 eim_a24 eim_bclk eim_d28 eim_a16 eim_a18 eim_oe eim_rw vdda eim_cs0 eim_da5 i2c1_dat dispb2_ser_dio ? clk_ss dispb2_ser_din por_b dispb2_ser_clk y aa dram_d11 dram_d10 dram_d4 dram_d5 nvcc_emi_dram ? gnd ? ? gnd ? ? gnd ? ? gnd ? ? gnd ? ? ckil ckih2 boot_mode1 reset_in_b aa table 133. 13 13 mm, 0.5 mm pitch ball map (continued) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
i.mx51 applications processors for consumer and industrial products, rev. 6 194 freescale semiconductor package information and contact assignments ab dram_d13 dram_d12 dram_d2 dram_d3 eim_lba eim_wait eim_a26 eim_d31 eim_a22 eim_d27 eim_d23 eim_d16 eim_eb2 eim_da8 eim_da6 eim_da3 jtag_tdi pmic_stby_req i2c1_clk vrefout tvdac_dhvdd ngnd_tv_back vdd_dig_pll_b ckih1 test_mode ab ac dram_d15 dram_d14 dram_d1 dram_d0 eim_dtack eim_a27 eim_cs4 eim_d30 eim_d25 eim_d19 eim_eb3 eim_da14 eim_da10 eim_da7 eim_da2 jtag_de_b jtag_tms pmic_int_req pmic_rdy comp fastr_dig nvcc_tv_back ngnd_osc vdd_ana_pll_b gnd_ana_pll_b ac ad gnd gnd vdd_dig_pll_a vdd_ana_pll_a eim_a25 eim_a21 eim_d29 eim_d26 eim_d18 eim_d20 eim_da15 eim_da13 eim_da9 eim_eb0 eim_da1 jtag_mod jtag_tdo jtag_tck ior_back iog_back iob_back nvcc_osc extal gnd_dig_pll_b gnd ad ae gnd gnd_dig_pll_a gnd_ana_pll_a eim_cs2 eim_a23 eim_a17 eim_a19 eim_d17 eim_d24 eim_d21 eim_d22 eim_da11 eim_da12 eim_eb1 eim_da0 eim_da4 jtag_trstb pmic_on_req ior iog iob fastr_ana xtal gnd gnd ae table 133. 13 13 mm, 0.5 mm pitch ball map (continued) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
package information and contact assignments i.mx51 applications processors for consumer and industrial products, rev. 6 freescale semiconductor 195 5.4 19 x 19 mm, 0.8 pitch ball map table 134 shows the 19 19 mm, 0.8 pitch ball map. table 134. 19 19 mm, 0.8 pitch ball map 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 a gnd nandf_cs5 nandf_d13 nandf_d8 nandf_d5 nandf_d2 nandf_d0 csi2_d19 aud3_bb_fs cspi1_sclk usbh1_data1 usbh1_data5 uart1_txd uart2_rxd str key_col1 sd1_clk sd1_data1 sd1_data3 csi1_hsync csi1_d9 gpio1_2 gnd a b nandf_cs3 nandf_cs4 nandf_rdy_int nandf_d14 nandf_d10 nandf_d6 nandf_d4 csi2_d12 aud3_bb_rxd cspi1_ss1 usbh1_dir usbh1_data2 usbh1_data6 uart1_cts uart3_txd key_row1 key_col3 sd2_clk sd2_data1 csi1_mclk gpio1_0 gpio1_4 gpio1_7 b c nandf_rb3 nandf_cs1 nandf_cs0 nandf_cs7 nandf_d12 nandf_d7 csi2_d13 aud3_bb_ck cspi1_rdy cspi1_miso usbh1_nxt usbh1_data3 usbh1_data7 uart2_txd key_row3 key_col5 sd2_data3 csi2_hsync gpio1_6 gpio1_9 gpio1_8 disp1_dat6 disp1_dat7 c d nandf_wp_b nandf_rb0 nandf_rb2 nandf_rb1 gpio_nand nandf_d15 nandf_d11 nandf_d3 csi2_d18 cspi1_mosi usbh1_clk usbh1_data4 uart1_rts key_row0 key_col2 sd1_data0 sd2_data2 gpio1_3 gpio1_5 gpio1_1 disp1_dat8 disp1_dat10 disp1_dat11 d e nandf_we_b nandf_re_b nandf_ale nandf_cs2 nandf_cs6 nvcc_nandf_a nandf_d9 nandf_d1 aud3_bb_txd cspi1_ss0 usbh1_stp usbh1_data0 uart1_rxd owire_line key_col0 sd1_cmd sd2_data0 csi1_d8 csi2_pixclk disp1_dat9 disp1_dat12 disp1_dat14 disp1_dat16 e f eim_sdba2 eim_sdodt1 eim_sdodt0 nandf_cle nvcc_nandf_a vddgp vddgp vddgp vddgp vddgp vddgp vddgp svddgp uart3_rxd key_row2 key_col4 sd1_data2 csi1_pixclk csi2_vsync disp1_dat13 disp1_dat17 disp1_dat22 disp1_dat20 f g dram_d28 dram_d29 dram_d30 dram_d31 gnd vddgp vddgp vdda nvcc_nandf_b nvcc_nandf_c nvcc_per11 nvcc_per12 nvcc_per13 nvcc_per17 nvcc_per5 nvcc_ipu4 sd2_cmd csi1_vsync disp1_dat15 disp1_dat18 disp1_dat23 di1_pin3 di1_pin2 g 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
i.mx51 applications processors for consumer and industrial products, rev. 6 196 freescale semiconductor package information and contact assignments h dram_d25 dram_d26 dram_sdqs3 dram_sdqs3_b dram_dqm3 nvcc_emi_dram vddgp vdda gnd nvcc_per9 nvcc_per10 vdda vcc svcc nvcc_per15 nvcc_per8 nvcc_ipu5 disp1_dat19 disp1_dat21 di1_pin15 di_gp1 di_gp3 di2_pin4 h j dram_sdqs2 dram_sdqs2_b dram_d22 dram_d23 dram_d27 nvcc_emi_dram vddgp gnd gnd gnd sgnd gnd gnd gnd vcc vcc nvcc_ipu6 di1_disp_clk di_gp2 di2_pin2 di2_disp_clk di_gp4 gpanaio j k dram_d19 dram_dqm2 dram_d20 dram_d21 dram_d24 nvcc_emi_dram vddgp gnd gnd gnd gnd gnd gnd gnd vcc vcc nvcc_ipu7 di2_pin3 rrefext vbus vreg dn dp k l dram_d18 dram_d17 dram_d16 dram_d15 dram_d14 nvcc_emi_dram vcc gnd gnd gnd gnd gnd gnd gnd vcc ngnd_usbphy nvcc_usbphy vdda33 id csi2_d14 csi2_d15 csi2_d16 csi2_d17 l m dram_d12 dram_dqm1 dram_d10 dram_d11 dram_d13 nvcc_emi_dram vcc vdda gnd gnd gnd gnd gnd gnd gnd nvcc_hs10 nvcc_hs6 nvcc_hs4_1 disp2_dat1 csi1_d14 csi1_d15 csi1_d18 csi1_d19 m n dram_d9 dram_d8 dram_sdqs1_b dram_sdqs1 dram_d7 nvcc_emi_dram vcc gnd gnd gnd gnd gnd gnd gnd gnd gnd vcc nvcc_hs4_2 disp2_dat6 disp1_dat0 disp1_dat1 csi1_d16 csi1_d17 n p dram_sdqs0_b dram_sdqs0 dram_dqm0 dram_d6 dram_d5 nvcc_emi_dram vcc gnd gnd gnd gnd gnd gnd gnd gnd vdda vcc nvcc_ipu8 disp2_dat8 disp2_dat2 disp2_dat3 csi1_d12 csi1_d13 p table 134. 19 19 mm, 0.8 pitch ball map (continued) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
package information and contact assignments i.mx51 applications processors for consumer and industrial products, rev. 6 freescale semiconductor 197 r dram_d3 dram_d2 dram_d1 dram_d4 vref nvcc_emi_dram vdd_fuse gnd gnd gnd gnd gnd gnd gnd gnd gnd vcc nvcc_ipu9 disp2_dat11 disp2_dat9 disp2_dat0 csi1_d10 csi1_d11 r t dram_d0 dram_a14 dram_sdclk dram_sdclk_b gnd nvcc_emi_dram gnd_dig_pll_a vcc vcc vcc vcc vcc vdda nvcc_i2c ngnd_tv_back gnd vcc nvcc_ipu2 disp2_dat13 di1_pin13 disp2_dat15 disp1_dat4 disp1_dat5 t u dram_a13 dram_a12 eim_sdba1 dram_a11 dram_sdwe vdd_dig_pll_a gnd_ana_pll_a nvcc_emi nvcc_emi nvcc_emi nvcc_emi nvcc_emi nvcc_per14 nvcc_srtc_pow vrefout nvcc_tv_back gnd_ana_pll_b nvcc_per3 dispb2_ser_din por_b di1_d0_cs disp1_dat2 disp1_dat3 u v eim_sdba0 dram_a10 dram_a9 dram_cas dram_a3 vdd_ana_pll_a nvcc_emi eim_d23 eim_eb3 eim_eb2 eim_da11 eim_eb0 eim_da1 jtag_mod jtag_tck tvdac_dhvdd ngnd_osc gnd_dig_pll_b ckih1 test_mode dispb2_ser_dio disp2_dat4 disp2_dat5 v w dram_ras dram_a8 dram_a6 dram_a4 dram_sdcke1 eim_cs0 eim_d31 eim_d27 eim_d21 eim_d17 eim_da13 eim_eb1 eim_da7 jtag_trstb i2c1_clk pmic_on_req nvcc_osc vdd_dig_pll_b vdd_ana_pll_b fastr_ana dispb2_ser_rs disp2_dat10 disp2_dat7 w y dram_a7 dram_a5 dram_cs1 dram_cs0 eim_dtack eim_cs1 eim_cs2 eim_d29 eim_d25 eim_d19 eim_da15 eim_da9 eim_da5 jtag_tdi pmic_stby_req ckil comp ahvddrgb ahvssrgb fastr_dig reset_in_b di1_pin11 disp2_dat12 y aa dram_sdcke0 dram_a1 dram_a2 eim_bclk eim_cs5 eim_cs4 eim_oe eim_a19 eim_a16 eim_d24 eim_d18 eim_da12 eim_da6 eim_da2 jtag_tdo pmic_int_req pmic_rdy ahvddrgb ahvssrgb ckih2 clk_ss di1_pin12 disp2_dat14 aa table 134. 19 19 mm, 0.8 pitch ball map (continued) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
i.mx51 applications processors for consumer and industrial products, rev. 6 198 freescale semiconductor package information and contact assignments ab dram_a0 eim_cre eim_rw eim_wait eim_a27 eim_a25 eim_a22 eim_a20 eim_a17 eim_d26 eim_d20 eim_da14 eim_da8 eim_da3 jtag_de_b i2c1_dat ior_back iog_back iob_back extal boot_mode0 boot_mode1 di1_d1_cs ab ac gnd eim_lba eim_cs3 eim_a26 eim_a24 eim_a23 eim_a21 eim_a18 eim_d30 eim_d28 eim_d22 eim_d16 eim_da10 eim_da4 eim_da0 jtag_tms ior iog iob xtal gnd dispb2_ser_clk gnd ac table 134. 19 19 mm, 0.8 pitch ball map (continued) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
revision history i.mx51 applications processors for consumer and industrial products, rev. 6 freescale semiconductor 199 6 revision history table 135 provides a revision history for this data sheet. 2 table 135. i.mx51 data sheet document revision history rev. number date substantive change(s) rev. 6 10 /2012 ? in t able 25, "i/o leakage current," on page 31 , updated supply rail names for sd1 and sd2 to nvcc_per15 an d nvcc_per17, respectively. ? updated section 4.6.7.3, ?general weim timing-synchronous mode.? ? updated section 4.6.7.4, ?examples of weim synchronous accesses.? ? updated section 4.6.7.5, ?general weim timing-asynchronous mode.? rev. 5 03/2012 ? in table 4, "jtag controller interface summary," on page 14 , changed on-chip termination column value for jtag_mod from ?100 k pull-down? to ?100 k pull-up.? ?in section 3.7, ?usb-otg iomux pin configuration,? removed the third sentence from the first paragraph and added a note after ta b l e 9 . ?in section 4.3.4, ?ultra-high voltage i/o (uhvio) dc parameters,? added clarification about uhvio i/o cell hve bit functionality after tab le 2 1 . ?in section 4.6.9, ?ddr2 sdram specific parameters : ? ?updated table 58, "ddr2 sdram timing parameter table," on page 69 ?added a note after ta b l e 5 8 ?updated figure 36, "ddr2 sdram write cycle timing diagram," on page 71 ?updated table 60, "ddr2 sdram write cycle parameter table," on page 71 ?added a note after ta b l e 6 0 ?updated figure 37, "ddr2 sdram dq versus dqs and sdclk read cycle timing diagram," on page 73 ?updated table 63, "ddr2 sdram read cycle parameter table," on page 73 ?added a note after ta b l e 6 3 ?in section 4.7.8.2, ?electrical characteristics,? changed signal name in the second sentence of the first paragraph from ?sensb_mclk? to ?sensb_pix_clk.? ?in table 128, "13 x 13 mm signal assignments, power rails, and i/o," on page 157 , changed configuraton after reset column value for contacts, di1_d0_cs, di1_d1_cs, di1_pin11, and di1_pin12, from ?low? to ?high.? ?in table 128, "13 x 13 mm signal assignments, power rails, and i/o," on page 157 , changed configuraton after reset column value for contact, jtag_mod, from ?100 k pull-down? to ?100 k pull-up.? ?in table 128, "13 x 13 mm signal assignments, power rails, and i/o," on page 157 , changed power rail column value for contacts, uart1_cts, uart1_rts, uart1_rxd, uart1_txd, uart2_rxd, uart2_txd, uart3_rxd, and uart3_txd, from ?nvvcc_per12? to ?nvcc_per12.? ?in table 131, "19 x 19 mm signal assignments, power rails, and i/o," on page 177 , changed configuraton after reset column value for contacts, di1_d0_cs, di1_d1_cs, di1_pin11, and di1_pin12, from ?low? to ?high.? ?in table 131, "19 x 19 mm signal assignments, power rails, and i/o," on page 177 , changed configuraton after reset column value for contact, jtag_mod, from ?100 k pull-down? to ?100 k pull-up.? ?in table 131, "19 x 19 mm signal assignments, power rails, and i/o," on page 177 , changed power rail column value for contacts, uart1_cts, uart1_rts, uart1_rxd, uart1_txd, uart2_rxd, uart2_txd, uart3_rxd, and uart3_txd, from ?nvvcc_per12? to ?nvcc_per12.? ?in table 132, "fuse override contacts," on page 189 : ?added a footnote for contact, disp1_dat6 ?removed information about contact, eim_a23, because the signal configuration it corresponds to, bt_hpn_en, is not in use. ? corrected cross-references throughout the document.
i.mx51 applications processors for consumer and industrial products, rev. 6 200 freescale semiconductor revision history rev. 4 08/2010 ? updated case temperature range column of table 1, "ordering information," on page 3 . ? updated table 13, "i.mx51 operating ranges," on page 19 to include separate specification for case temperature for industrial parts. ? removed table footnote in table 16, "i.mx51 stop mode current and power consumption," on page 21 . ? removed table footnote in table 47, "camp electrical parameters (ckih1, ckih2)," on page 48 . ? updated table 52, "weim interface pinout in various configurations," on page 55 . rev. 3 06/2010 ? updated max column of table 15, "fuse supply current," on page 21 . deleted efuse read current row from the same table. ? updated symbol, test conditions, and max columns of table 18, "gpio/hsgpio dc electrical characteristics," on page 25 . ? updated max and unit columns of table 19, "ddr2 i/o dc electrical parameters," on page 26 . ? updated test conditions, max, and unit columns of table 20, "lvio dc electrical characteristics," on page 26 ? updated symbol, test conditions, max, and unit columns of table 21, "uhvio dc electrical characteristics," on page 27 . ? updated max and unit columns of table 22, "i2c standard/fast/high-speed mode electrical parameters for low/medium drive strength," on page 29 . ? added a new table table 25, "i/o leakage current," on page 31 . table 135. i.mx51 data sheet document revision history (continued) rev. number date substantive change(s)
revision history i.mx51 applications processors for consumer and industrial products, rev. 6 freescale semiconductor 201 rev. 2 05/2010 ? updated casetemperature range column in table 1, "ordering information," on page 3 . ? changed the vrefout column in table 3, "special signal considerations," on page 12 . ? added section 3, ?iomux configuration for boot media? . ? updated figure 2, "power-up sequence," on page 24 . ? updated the minimum and maximum columns in table 13, "i.mx51 operating ranges," on page 19 . ? added a note in section 4.2.1, ?power-up sequence? . ? updated section 4.2.1, ?power-up sequence . ? ? changed the input current (47 k pull-up) column in table 21, "uhvio dc electrical characteristics," on page 27 to input current (75 ko pull-up). ? added new table for parameters for ddr2 pad output buffer impedance. see table 27, "ddr2 i/o output buffer impedance hve = 0," on page 32 . ? added new section under section 4.5, ?i/o ac parameters? . see section 4.5.4, ?ac electrical characteristics for ddr2?. ? updated table 47, "camp electrical parameters (ckih1, ckih2)," on page 48 . in the vih (for square wave input) parameter, the minimum frequency was changed to nvcc_per3 - 0.25v and the maximum frequency was changed to nvcc_per3. ? added a note in section 4.6.6, ?nand flash controller (nfc) parameters ? after ta b l e 4 9 . ? updated asymmetric mode min, symmetric mode min, and max columns of ta b l e 5 0 . ? removed conditions parameters of the full scale output voltage row in ta b l e 8 2 . ? updated section 4.7.11, ?p-ata timing parameters? . replaced ata/atapi-6 specification with ata/atapi-5 specification. ?in table 102, "ssi transmitter timing with internal clock," on page 135 , under the synchronous internal clock operation sections for the id ss42, minimum frequency was changed from 10.0 to 30. ?in table 103, "ssi receiver timing with internal clock," on page 136 , under the internal clock operation section for id ss20, minimum frequency was changed from 10.0 to 30. ?in table 104, "ssi transmitter timing with external clock," on page 138 , under the external clock operation section for id ss38, maximum frequency was changed from 15.0 to 30. ? added a new section section 4.7.16.1, ?uart electrical? , under section 4.7.16, ?uart? . ?in table 118, "usb port timing specification in vp_vm bi-directional mode," on page 148 , for ids ss28 and ss29, direction was changed from out to in. ?in table 120, "usb timing specification in vp_vm unidirectional mode," on page 150 , for ids us40 and us41, direction was changed from out to in and the reference signal was changed to usb_vm1 and usb_vp1 respectively. ?in table 122, "usb timing specification for ulpi parallel mode," on page 151 , added an extra row for id17. ? updated signal and direction columns in table 120, "usb timing specification in vp_vm unidirectional mode," on page 150 . ? updated signal names in table 118, "usb port timing specification in vp_vm bi-directional mode," on page 148 . rev. 1 10/2009 initial public release. table 135. i.mx51 data sheet document revision history (continued) rev. number date substantive change(s)
document number: imx51cec rev. 6 09/2012 how to reach us: home page: freescale.com web support: freescale.com/support information in this document is provided solely to enable system and software implementers to use freescale products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits based on the information in this document. freescale reserves the right to make changes without further notice to any products herein. freescale makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does freescale assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters that may be provided in freescale data sheets and/or specifications can and do vary in different applications, and actual performance may vary over time. all operating parameters, including ?typicals,? must be validated for each customer application by customer?s technical experts. freescale does not convey any license under its patent rights nor the rights of others. freescale sells products pursuant to standard terms and conditions of sale, which can be found at the following address: freescale.com/salestermsandconditions. freescale and the freescale logo are trademarks of freescale semiconductor, inc. reg. u.s. pat. & tm. off. all other product or service names are the property of their respective owners. arm is the registered trademark of arm limited. arm cortex tm -a8 is the trademark of arm limited. ? 2012 freescale semiconductor, inc. all rights reserved.

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